ESD protection circuit for different power supplies

A voltage clamping circuit connected between a first power supply voltage terminal and a second power supply voltage terminal to prevent a differential voltage developed between the first power supply terminal and the second power supply terminal from exceeding a first clamping voltage level and a second clamping voltage level, comprising:

• a first subgroup of Darlington connected clamping transistors connected between the first power supply voltage terminal and the second power supply voltage terminal, whereby if the differential voltage exceeds the first clamping voltage level, said first subgroup of Darlington connected clamping transistors turn on and restore said first differential voltage to a level less than the first clamping voltage level;
• and
• a second subgroup of Darlington connected clamping transistors connected between the second power supply terminal and the first power supply terminal, whereby if the differential voltage exceeds the second clamping voltage level, said second subgroup of Darlington connected transistors turn on and restore said differential voltage to a level less than the second clamping voltage level;
• wherein each clamping transistor comprises:
• a collector well of a first conductivity type having a first concentration diffused in a surface of a semiconductor substrate;
• at least one collector contact region of the first conductivity type having a second concentration that is greater than the first concentration diffused into said surface of the semiconductor substrate within said collector well to form a first low resistivity contact to said collector well;
• a base well of a second conductivity type, having a third concentration diffused into said surface of the semiconductor substrate within said collector well;
• a base contact of the second conductivity type, having a fourth concentration that is greater than the third concentration, diffused into said surface of the semiconductor substrate within said base well to form a second low resistivity contact to said base well;
• and
• an emitter region of the first conductivity type of the second concentration diffused into said surface of the semiconductor substrate within the base well.