US 6,271,705 B1Granted

Data output circuits having enhanced ESD resistance and related methods

AssigneeSamsung Electronics Co., Ltd.

InventorsYoung-Ho Suh, Choong-Keun Kwak, Sang-Jib Han

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Abstract

A data output circuit includes a periphery circuit connected between a supply voltage and a first ground voltage line and an output driver connected between a supply voltage and a second ground voltage line. The periphery circuit receives a first input signal and generates a first output signal on a node responsive to the first input signal, and the output driver receives a second input signal and the first output signal and generates a second output signal on an output pin in response thereto. A discharge circuit is coupled with the first ground voltage line wherein the discharge circuit allows current to flow from the first ground voltage line and wherein the discharge circuit blocks current flow to the first ground voltage line. Related methods are also discussed.

Claims42

Dependent claims

A data output circuit for an integrated circuit memory device, said data output circuit comprising:

a periphery circuit coupled between a supply voltage and a first ground voltage line wherein said periphery circuit receives a first input signal and generates a first output signal on a node responsive to said first input signal wherein said periphery circuit comprises first and second periphery MOS transistors serially coupled between said supply voltage and said first ground voltage line, wherein said first input signal is provided to gates of each of said periphery MOS transistors, and wherein said output node is connected between said first and second periphery MOS transistors wherein said first periphery MOS transistor comprises a PMOS transistor and said second periphery MOS transistor comprises an NMOS transistor wherein said first periphery MOS transistor is coupled to said supply voltage and said second periphery MOS transistor is coupled to said first ground voltage line;
an output driver coupled between said supply voltage and a second ground voltage line wherein said output driver receives a second input signal and said first output signal, and generates a second output signal on an output pin in response thereto wherein said output driver comprises first and second driver MOS transistors serially coupled between said supply voltage and said second ground voltage line, wherein said second input signal is provided to a Rate of said first driver MOS transistor, wherein said output node is coupled with a gate of said second driver MOS transistor, and wherein an output pin is coupled between said first and second driver MOS transistors wherein said first driver MOS transistor comprises a PMOS transistor and said second driver MOS transistor comprises an NMOS transistor wherein said first driver MOS transistor is coupled to said supply voltage and said second driver MOS transistor is coupled to said second ground voltage line;
and
a discharge circuit coupled to said first ground voltage line wherein said discharge circuit allows a forward current to flow from said first ground voltage line and wherein said discharge circuit blocks a reverse current flow to said first ground voltage line.

1 more element

A data output circuit for an integrated circuit memory device, said data output circuit comprising:

a periphery circuit coupled between a supply voltage and a first ground voltage line wherein said periphery circuit receives a first input signal and generates a first output signal on a node responsive to said first input signal wherein said periphery circuit comprises first and second periphery MOS transistors serially coupled between said supply voltage and said first ground voltage line, wherein said first input signal is provided to said gates of each of said periphery MOS transistors, and wherein said output node is connected between said first and second periphery MOS transistors wherein said first periphery MOS transistor comprises a PMOS transistor and said second periphery MOS transistor comprises an NMOS transistor wherein said first periphery MOS transistor is coupled to said supply voltage and said second periphery MOS transistor is coupled to said first ground voltage line;
an output driver coupled between said supply voltage and a second ground voltage line wherein said output driver receives a second input signal and said first output signal and generates a second output signal on an outut pin in response thereto wherein said output driver comprises first and second driver MOS transistors serially coupled between said supply voltage and said second ground voltage line, wherein said second input signal is provided to a gate of said first driver MOS transistor, wherein said output node is coupled with a gate of said second driver MOS transistor, and wherein an output pin is coupled between said first and second driver MOS transistors wherein said first driver MOS transistor comprises a PMOS transistor and said second driver MOS transistor comprises an NMOS transistor wherein said first driver MOS transistor is coupled to said supply voltage and said second driver MOS transistor is coupled to said second ground voltage line and
a discharge circuit coupled between said first ground voltage line and said output pin wherein said discharge circuit allows a forward current to flow from said first ground voltage line to said output pin when a voltage difference therebetween exceeds a predetermined threshold and wherein said discharge current blocks a reverse current flow from said output pin to said first ground voltage line.

Dependencies are inferred from the claim text.