Method for elimination of parasitic bipolar action in silicon on insulator (SOI) dynamic logic circuits
AssigneeInternational Business Machines Corporation
InventorsJeff Van Tran, Salvatore N. Storino
Life of this patent
Estimating the term…
Abstract
The present invention is an apparatus and method to overcome the unwanted effects of parasitic bipolar discharge in silicon-on-insulator (SOI) field effect transistors (FET) by expanding a stack SOI MOS devices arranged to provide a predetermined logic function. The SOI MOS devices are arranged so as to eliminate electrical connections between certain intermediate nodes of the dynamic logic circuit. Accordingly, eliminating any parasitic bipolar current leakage paths associated with such electrical connections between certain intermediate nodes of said stacked SOI MOS devices of said dynamic circuit.
Claims22
A method of providing a Silicon on Insulator (SOI) Metal Oxide Semiconductor (MOS) dynamic logic circuit for implementing a logic function, said dynamic logic circuit having an output device and a shared node providing input to said output device, the method comprising:
- providing a plurality of stacks connected in parallel with one another and between said shared node and a common discharge potential to perform a predetermined logic function, each stack comprising a respective plurality of stacked SOI MOS devices and at least one intermediate node;
- providing a respective active discharging device interconnected between each said intermediate node and said common discharge potential, each said active discharging device being controlled by a corresponding input to a respective one of said stacked SOI MOS devices to discharge the corresponding intermediate node to said common discharge potential;
- wherein said plurality of stacks are arranged so as to eliminate any parasitic bipolar transistor current leakage path.
A method of eliminating parasitic bipolar transistor action in an apparatus including a dynamic logic circuit performing a predetermined logic output function, the dynamic logic circuit further including a plurality of Silicon on Insulator (SOI) Metal Oxide Semiconductor (MOS) devices, the dynamic logic circuit defining a plurality of interconnected intermediate nodes providing an electrical conductive path between the intermediate nodes, the method comprising:
- providing a stack expansion of a plurality of said SOI MOS devices;
- eliminating said conductive path between said nodes coupling said SOI MOS devices;
- and
- maintaining said predetermined logic output function;
- whereby said parasitic bipolar action of said SOI MOS devices are deactivated.
Dependencies are inferred from the claim text.