Belowground and oversupply protection of junction isolated integrated circuits

An integrated circuit with junction isolation comprising:

• a substrate having a first conductivity type;
• at least one first and at least one second DMOS power transistors formed in respective first and second regions of a second conductivity type on said substrate, said at least one first DMOS power transistor being connected to a voltage supply and said at least one second DMOS power transistor being connected to ground;
• at least one circuit formed in a third region on said substrate, said at least one circuit being sensitive to oversupply and belowground effects induced by said at least one first and at least one second DMOS power transistors;
• and
• an oversupply protection circuit for controlling the oversupply effects induced by said at least one first DMOS power transistor;
• the first region being interposed between the third region and the second region and having a predetermined shape so that the belowground effects induced by said at least one second DMOS power transistor in the second region are attenuated by a layout separation resulting from the predetermined shape of the interposed first region.

An integrated circuit with junction isolation comprising:

• a substrate having a first conductivity type;
• at least one first and at least one second DMOS power transistors formed in respective first and second regions of a second conductivity type on said substrate, said at least one first DMOS power transistor being connected to a voltage supply and said at least one second DMOS power transistor being connected to ground;
• at least one circuit formed in a third region on said substrate, said at least one circuit being sensitive to oversupply and belowground effects induced by said at least one first and at least one second DMOS power transistor;
• and
• a dummy biased isolation region on said substrate being interposed between the third region and the first and second regions and having a predetermined shape so that the oversupply and belowground effects induced by said at least one first and at least one second DMOS power transistors to said at least one circuit are attenuated by a layout separation resulting from the predetermined shape of the interposed dummy biased isolation region.