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US 6,271,563 B1Granted
MOS transistor with high-K spacer designed for ultra-large-scale integration
AssigneeAdvanced Micro Devices, Inc.
InventorsBin Yu, Ming-Ren Lin
Life of this patent
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Abstract
A MOS transistor having a source and drain extension that are less than 40 nanometers in thickness to minimize the short channel effect. A gate includes a high-K dielectric spacer layer to create depletion regions in the substrate which form the drain and source extensions.
Claims13
A MOS transistor comprising:
- a source well and a drain well formed in a semiconductor substrate and defining a channel therebetween;
- a gate stack including a gate oxide formed on a surface of the semiconductor substrate over a portion of the channel and a gate on the gate stack;
- and
- a first spacer positioned on the surface of the semiconductor substrate on a source side of the gate stack over a source extension region in the channel between the source well and the gate stack in the semiconductor substrate and a second spacer positioned on the surface of the semiconductor substrate on a drain side of the gate stack over a drain extension region in the channel between the drain well and the gate stack in the semiconductor substrate, the first spacer and the second spacer being formed of a relatively high-K dielectric material to invert the surface of the semiconductor substrate in the source extension region and the drain extension region even when no voltage is applied to the gate stack of the MOS transistor,
- wherein said gate is on said high-K dielectric material on said source side and said drain side.
2 more elements
A MOS transistor comprising:
- a source well located in a substrate;
- a drain well located in the substrate;
- a channel located in the substrate between the source well and the drain well wherein the channel separates the source and drain wells;
- a source extension region located in a portion of the channel adjacent to the source well;
- a drain extension region located in a portion of the channel adjacent to the drain well;
- a gate including a gate oxide layer disposed on a surface of the substrate and a polysilicon layer electrically isolated from channel by the gate oxide layer, the gate being located over a portion of the channel between the source extension region and the drain extension region;
- and
- a spacer layer disposed on the surface of the substrate on a source side and a drain side of the gate, the spacer layer being formed of a high-K material to have an equivalent electrical thickness less than an electrical thickness of the gate oxide layer so that the surface of the substrate in the source extension region and the drain extension region is inverted when no voltage is applied to the gate,
- wherein said polysilicon layer is on said high-K material on said source side and said drain side.
6 more elements
Dependencies are inferred from the claim text.