Method for fabricating floating gate semiconductor devices with trench isolation structures and self aligned floating gates

A floating gate semiconductor device comprising:

• a semiconductor substrate having a surface;
• a field effect transistor on the substrate comprising a gate dielectric layer and spaced source/drain regions on opposing sides thereof;
• a pair of spaced isolation structures in the substrate electrically isolating the field effect transistor from adjacent field effect transistors on the substrate, each isolation structure located on a side of the transistor proximate to a source/drain region, the pair of spaced isolation structures comprising an electrically insulating material configured to form a recess at least partially enclosing the transistor and having endpoints with a height relative to the surface;
• a floating gate on the gate dielectric layer comprising a conductive layer within the recess planarized to the endpoints of the isolation structures;
• a control gate dielectric layer on the floating gate;
• and
• a control gate on the control gate dielectric layer.

A semiconductor array comprising:

• a semiconductor substrate having a surface;
• a plurality of active areas on the substrate, each active area comprising spaced source/drain regions on opposing sides thereof;
• a plurality of electrically insulating isolation structures in the substrate electrically insulating the active areas from one another, each isolation structure located on a side of an active area proximate to a source/drain region forming a plurality of recesses at least partially enclosing the active areas and having endpoints with a height relative to the surface;
• and
• a plurality of floating gates on the substrate comprising conductive layers within the recesses planarized to the endpoints of the isolation structures.

A semiconductor array comprising:

• a semiconductor substrate comprising a gate dielectric layer;
• a plurality of field effect transistors on the substrate comprising sources and drains electrically connected to form bit lines, each transistor comprising a source/drain region on opposing sides thereof;
• a plurality of isolation structures in the substrate configured to electrically insulate the transistors from one another, each isolation structure located on a side of a transistor, the isolation structures comprising an electrically insulating material having a height with respect to the gate dielectric layer and forming a plurality of recesses at least partially enclosing the transistors;
• a plurality of floating gates within the recesses comprising a plurality of conductive layers planarized to endpoints of the isolation structures;
• a plurality of control gate dielectric layers on the floating gates;
• and
• a plurality of control gates on the control gate dielectric layers and configured as word lines.