High density memory structure
AssigneeMosel Vitelic, Inc.
InventorsMin-Liang Chen, Nan-Hsiung Tsai
Life of this patent
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Abstract
A dynamic random access memory (DRAM) integrated circuit (10). The DRAM (10) includes a recessed region (20) defined in a semiconductor substrate (22). This recessed region has substantially vertical sides (34) extending from a bottom surface (32). A field effect transistor (18) is defined adjacent to the recessed region (20). A capacitor structure, including a lower capacitor plate (26), a capacitor dielectric (28), and an upper capacitor plate (30), is defined in the recessed region (20) and over the field effect transistor (18), thereby providing a greater capacitor surface.
Claims7
An integrated circuit comprising:
- a semiconductor substrate;
- a first recessed region and a second recessed region in said semiconductor substrate, said first recessed region having sides extending from a first bottom surface, said second recessed region having sides extending from a second bottom surface;
- a first insulating layer adjacent to said semiconductor substrate and covering said first bottom surface and a portion of at least one of said sides of said first recessed region, and a second insulating layer defined overlying said second recessed region;
- a field effect transistor, said field effect transistor including a first source/drain region adjacent to said first recessed region and a second source/drain region adjacent to said second recessed region;
- a first conductor defined within said first recessed region, said first conductor being coupled to said first source/drain region to define a bit-line structure;
- and
- a second conductor defined within said second recessed region, said second conductor being coupled to said second source/drain region to define a capacitor structure.
Dependencies are inferred from the claim text.