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AssigneeInternational Business Machines Corporation
InventorsPhilip George Emma, Wei Hwang, Stephen McConnell Gates
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The present invention describes the use of two semiconductor layers, a thin film (TF) layer and a bulk Si wafer layer, to make high density and high speed merged logic and memory IC chips. The memory cells use three-dimensional (3D) SRAM structures. Two kinds of 3D logic cells are disclosed. 3D form of the differential cascode voltage switch (DCVS) architecture, and a 3D form of the DCVS with pass gate (DCVSPG) logic architecture. A high density “system on chip” architecture is described. The high density is achieved by locating large PMOS transistors in the TF Si layer, and the fast NMOS transistors in a bulk Si wafer layer. A single process sequence to simultaneously make the logic and memory circuits on the IC chip is also described.
A plurality of transistors made in two distinct semiconductor levels, a bulk silicon (Si) and a thin film Si level, in a single integrated circuit (IC) chip, each said transistor being in a single one of said levels and connected to form logic circuits in selected regions of the IC chip and to form static random access memory (SRAM) arrays in the remaining regions of the IC chip, wherein said logic circuits and said memory devices are logically interconnected, said selected regions being arbitrarily selectable in blocks as small as six transistors.
Dependencies are inferred from the claim text.