Locally confined deep pocket process for ULSI mosfets
AssigneeAdvanced Micro Devices, Inc.
InventorBin Yu
Life of this patent
Estimating the term…
Abstract
A method of fabricating an integrated circuit with locally confined deep pocket regions utilizes a dummy or sacrificial gate spacer. Dopants are provided through the openings associated with sacrificial spacers to form the pocket regions. The dopants are provided after silicidation. The openings can be filled with spacers. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS).
Claims22
A method of manufacturing an integrated circuit, comprising:
- providing a gate structure between a source region and a drain region in a semiconductor substrate, the gate structure including a plurality of dielectric spacers;
- removing the dielectric spacers, thereby exposing the semiconductor substrate at a first location and a second location;
- and
- providing an ion implant at the first location and at the second location to form deep pocket regions, the deep pocket regions having a somewhat lemon-drop shape, the deep pocket regions defining a V-shaped boundary underneath the gate structure and above the deep pocket regions, whereby a channel region underneath the gate structure has a two dimensional channel doping profile.
A method of manufacturing an ultra-large scale integrated circuit including a plurality of field effect transistors having locally confined pocket regions, the method comprising steps of:
- forming at least part of a gate structure on a top surface of a semiconductor substrate and between a source and a drain, the gate structure including a pair of spacers;
- forming a silicide over at least the source and the drain;
- removing the pair of spacers;
- and
- providing a dopant at a first location and a second location associated with the spacers, thereby forming the locally confined pocket regions, the pocket regions defining a curved V-shaped boundary for a channel underneath the gate structure and above the pocket regions.
A process for forming a first pocket region at least partially below a shallow source extension and a second pocket region at least partially below a shallow drain extension, the process comprising:
- forming a plurality of gate structures on a top surface of a substrate, each of the gate structures including a pair of dummy spacers;
- stripping the dummy spacers, thereby forming openings to the substrate;
- and
- providing a dopant through the openings to the substrate, thereby forming the first pocket region and the second pocket region, the first pocket region and the second pocket region defining a curved V-shaped boundary underneath each of the gate structures and above the first pocket region and the second pocket region.
A method of manufacturing an integrated circuit including a source region and a drain region in a semiconductor substrate, the method comprising:
- providing a silicide layer over the source region and the drain region and a gate having spacers;
- removing said spacers to expose the semiconductor substrate at a first location and a second location;
- and
- providing an ion implant at the first location to form a first deep pocket region and at the second location to form a second deep pocket region, the first deep pocket region extending below the drain region and the second deep pocket region extending below the source region, wherein the first pocket region and the second pocket region define a curved V-shaped border underneath the gate structure and above the first pocket region and the second pocket region the V-shaped border being exclusive of the first location and the second location.
Dependencies are inferred from the claim text.