Method of manufacturing flash memory

A method of manufacturing a flash memory having a dual floating gate structure, comprising the steps of:

• providing a substrate having a plurality of source/drain regions formed therein;
• forming a first conductive layer formed on the substrate between the source/drain regions, wherein a first dielectric layer is located between the substrate and the first conductive layer;
• forming a floating gate mask on the substrate and the first conductive layer to expose a portion of the first conductive layer;
• removing the portion of the first conductive layer and a portion of the first dielectric layer beneath the exposed conductive layer until a portion of the substrate between the source/drain regions is exposed, wherein a remaining first conductive layer regarded as a dual floating gate comprising a first floating gate partially covering one source/drain region and a second floating gate partially covering the other source/drain region;
• removing the floating gate mask;
• forming a conformal second dielectric layer and a second conductive layer over the substrate in sequence;
• and
• patterning the second conductive layer and the second dielectric layer to respectively form a control gate and a third dielectric layer.