Structure and method for planar MOSFET DRAM cell free of wordline gate conductor to storage trench overlay sensitivity

A method of forming a memory cell in a semiconductor substrate, said memory cell comprising trench capacitors, transfer transistors, bitlines and wordlines, said method comprising the steps of:

• (a) forming a stack of at least four material layers on a surface of a semiconductor substrate, wherein at least two of said material layers of said stack are selectively etchable relative to each other;
• (b) patternwise etching through said stack to define a critical pattern of remaining stack and spaces where said semiconductor substrate is exposed, said critical pattern defining possible locations for trench capacitors and gate conductors;
• (c) filling said spaces with a filler material which is selectively etchable relative to a topmost layer of said remaining stack;
• (d) planarizing the filler material stopping at said topmost layer of said remaining stack;
• (e) forming trench capacitors in said semiconductor substrate by etching through portions of said filler material and said substrate, wherein said etching removes a portion of said topmost layer of said remaining stack and exposes a portion of a layer of said stack that is next to the topmost layer;
• (f) planarizing the remaining portion of said stack and filler material to remove the remaining portion of the topmost layer of said stack and the remaining portion of the layer that is next to the topmost layer and thereby exposing a layer of said stack that is second from the topmost layer;
• (g) replacing at least a portion of either said remaining stack, said remaining filler material or both with a placeholder material corresponding to locations for gate conductors;
• and
• (h) forming said gate conductors and remaining portions of said transistors, bitlines and wordlines of said memory cell.