Methods for running a high density plasma etcher to achieve reduced transistor device damage

A method for etching dielectric layers in a high density plasma etcher, comprising:

• providing a wafer having a photoresist mask over a dielectric layer in order to define at least one contact via hole over at least one transistor diffusion region;
• inserting the wafer into the high density plasma etcher;
• pulse applying a TCP source of the high density plasma etcher, wherein the pulse applying includes,
• ascertaining an etch performance characteristic, including photoresist selectivity and etch rate which is associated with a continuous wave application of the TCP source;
• selecting a duty cycle of the pulsed application of the TCP source;
• and
• scaling a peak power of the pulsed application of the TCP source in order to match a cycle-averaged power that would be delivered by the continuous wave application of the TCP source, wherein the scaling is designed to vary the peak power of the pulse application of the TCP source inversely to the duty cycle;
• wherein the pulsed application of the TCP source is configured to etch through the dielectric layer down to the at least one transistor diffusion region while substantially reducing damage to transistor gate oxides of transistor devices that are defined on the wafer.

A method for etching dielectric layers in a high density plasma etcher, comprising:

• providing a wafer having a photoresist mask over a dielectric layer in order to define at least one via hole or open area that is electrically interconnected down to a silicon substrate of the wafer, the dielectric layer being any layer of wafer;
• inserting the wafer into the high density plasma etcher;
• pulse applying a TCP source of the high density plasma etcher, wherein the pulse applying includes,
• ascertaining an etch performance characteristic, including photoresist selectivity and etch rate which is associated with a continuous wave application of the TCP source;
• selecting a duty cycle of the pulsed application of the TCP source;
• and
• scaling a peak power of the pulsed application of the TCP source in order to match a cycle-averaged power that would be delivered by the continuous wave application of the TCP sources, wherein the scaling is designed to vary the peak power of the pulse application of the TCP source inversely to the duty cycle;
• wherein the pulsed application of the TCP source is configured to etch the via hole through the dielectric layer while substantially reducing damage to transistor gate oxides of transistor devices formed over the wafer.