Polysilicon structure and process for improving CMOS device performance

A process for depositing polycrystalline silicon, comprising:

• exposing a semiconductor substrate on which the polycrystalline silicon is to be deposited to a silane gas and a temperature of about 680° C. to about 800° C., wherein the silane gas is introduced in to the processing chamber at a flow rate of about 500 sccm.

A process for depositing polycrystalline silicon, comprising:

• exposing a semiconductor substrate on which the polycrystalline silicon is to be deposited to a silane gas and a temperature of about 680° C. to about 800° C.;
• and
• introducing hydrogen gas into the processing chamber at a flow rate of about 9850 sccm.

A process for depositing polycrystalline silicon, comprising:

• exposing a semiconductor substrate on which the polycrystalline silicon is to be deposited to a silane gas and a temperature of about 680° C. to about 800° C.;
• and
• introducing hydrogen gas into the processing chamber at a flow rate of about 10 liters per minute.

A process for depositing polycrystalline silicon, comprising:

• exposing a semiconductor substrate on which the polycrystalline silicon is to be deposited to a silane gas and a temperature of about 680° C. to about 800° C., wherein the process produces a deposition rate of polycrystalline silicon of about 5000 Å per minute to about 6000 Å per minute.

A process for depositing polycrystalline silicon, comprising:

• exposing a semiconductor substrate on which the polycrystalline silicon is to be deposited to a silane gas and a temperature of about 680° C. to about 800° C., wherein the process produces a deposition rate of polycrystalline silicon of about 5217 Å per minute.

A process for depositing polycrystalline silicon, comprising:

• exposing a semiconductor substrate on which the polycrystalline silicon is to be deposited to a silane gas and a temperature of about 680° C. to about 800° C., wherein the process forms a gate of a CMOS device, and wherein the CMOS device is a PFET and the deposited polycrystalline silicon produces a saturated device current of about 367 μamps/μm to about 377 μamps/μm.

A process for depositing polycrystalline silicon, comprising:

• exposing a semiconductor substrate on which the polycrystalline silicon is to be deposited to a silane gas and a temperature of about 680° C. to about 800° C., wherein the process forms a gate of a CMOS device, and wherein the CMOS device is a PFET and the deposited polycrystalline silicon produces a saturated device current of about 690 μamps/μm to about 700 μamps/μm.

A process for depositing polycrystalline silicon, comprising:

• exposing a semiconductor substrate on which the polycrystalline silicon is to be deposited to a silane gas and a temperature of about 680° C. to about 800° C., wherein susceptibility to polycrystalline silicon depletion is reduced.