Asic routing architecture

A semiconductor chip, comprising:

• a prefabricated substantially channel-less array of function blocks, which function blocks are couplable to form an arbitrary circuit, wherein each function block includes a plurality of semiconductor devices formed with a substrate;
• at least one prefabricated conducting layer that forms at least one connection among said semiconductor devices within each function block thereby forming a respective function block circuit within each respective function block, where each function block has at least one of an input or an output;
• a first insulating layer formed over said at least one conducting layer;
• a prefabricated fixed conducting layer formed over said first insulating layer and substantially over a space occupied by at least some of said function blocks, said fixed conducting layer including a first plurality of parallel segmented conductors extending in a first direction, and wherein said prefabricated fixed conducting layer further includes a plurality of pin connectors to respective ones of said inputs and outputs, said at least some of said function blocks usable in said arbitrary circuit;
• a second insulating layer formed over said prefabricated fixed conducting layer;
• a customized conducting layer used to form said arbitrary circuit and formed over said second insulating layer, wherein said customized conducting layer is substantially formed within a plurality of parallel tracks and over said first plurality of parallel segmented conductors in a second direction substantially perpendicular to said first direction;
• and
• wherein at least some segments formed by said first plurality of parallel segmented conductors in said fixed conducting layer are coupled to a respective via formed through said second insulating layer.

A semiconductor chip, comprising:

• a substantially channel-less array of function blocks, which function blocks are couplable to form an arbitrary circuit, wherein each function block includes a plurality of semiconductor devices formed with a substrate, at least some of said function blocks to be used function blocks;
• at least one prefabricated conducting layer that forms connections among said semiconductor devices within each function block thereby forming a respective function block circuit within each respective function block, where each function block circuit has at least one of an input or an output;
• a first insulating layer formed over said at least one prefabricated conducting layer;
• a fixed conducting layer formed over said first insulating layer and formed substantially over a space occupied by said used function blocks, said fixed conducting layer formed independent of any channels dividing said function blocks and independent of said arbitrary circuit, said fixed conducting layer including a first plurality of parallel segmented conductors extending in a first direction, wherein each of said parallel segmented conductors in said first plurality of parallel segmented conductors includes at least a long segment and a short segment, wherein each segment of each conductor has a first end and a second end, and wherein said short segment is coupled to a respective pin connector in a plurality of pin connectors, which are coupled to respective ones of said inputs and outputs;
• a second insulating layer formed over said fixed conducting layer;
• a customized conducting layer formed over said second insulating layer, wherein said customized metal layer is substantially formed within a plurality of predesignated parallel tracks and over said first plurality of parallel segmented conductors in a second direction substantially perpendicular to said first direction;
• wherein each segment formed by said first plurality of parallel segmented conductors in said fixed conducting layer is coupled at said first end to a respective first via formed through said second insulating layer and each segment is further coupled at said second end to a second respective via formed through said second insulating layer;
• wherein each of said long segments is coupled between said first end and said second end to an additional via formed through said second insulating layer;
• wherein said plurality of predesignated parallel tracks are positioned in pairs, wherein each pair of tracks lies in a space between a respective pair of vias formed through said second insulating layer, and wherein one pair of tracks is positioned over said short segment, said one pair of tracks predesignated as a power line and a ground line.

A customizable semiconductor chip, comprising:

• a prefabricated substantially channel-less array of function blocks, which function blocks are couplable to form an arbitrary circuit, and wherein each function block includes a plurality of semiconductor devices formed with a substrate;
• at least one prefabricated conducting layer that forms connections among said semiconductor devices within each function block thereby forming a respective function block circuit within each respective function block where each function block has at least one of a defined input or a defined output;
• a first insulating layer formed over said at least one prefabricated conducting layer;
• a prefabricated fixed conducting layer formed over said first insulating layer and substantially over a space occupied by at least some of said function blocks, said prefabricated fixed conducting layer including a first plurality of parallel segmented conductors extending in a first direction, and wherein said prefabricated fixed conducting layer further includes a plurality of pin connectors to respective ones of said inputs and outputs, said at least some of said function blocks usable in said arbitrary circuit;
• said prefabricated fixed conducting layer for use with a customizable conducting layer to be selectively formed in locations over a second insulating layer and said prefabricated fixed conducting layer, said fixed conducting layer and said customizable conducting layer for interconnecting said function blocks.

A process for forming an integrated circuit, comprising:

• (a) forming a plurality of semiconductor devices with a substrate, said semiconductor devices organized in a plurality of function blocks;
• (b) interconnecting said semiconductor devices within each function block thereby forming a respective function block circuit within each respective function block, where each function block has at least one of an input or an output;
• (c) forming a function block interconnect structure independent of any channels dividing said function blocks including the steps of:
• (1) forming &fixed conducting layer substantially over a space occupied by said function blocks, said fixed conducting layer including a plurality of parallel segmented conductors, and wherein said fixed conducting layer further includes a plurality of pin connectors to respective ones of said inputs and outputs, said fixed conducting layer independent of any circuit ultimately formed by said function block interconnect structure;
• (2) forming at least an insulating layer, said insulating layer having vias therethrough coupled to respective segments formed by said plurality of parallel segmented conductors in said fixed conducting layer;
• (3) forming a customized conducting layer, wherein at least a portion of said customized conducting layer is formed within a plurality of parallel tracks and over said space occupied by said function blocks, and at least a second portion of said customized conducting layer is in electrical communication with at least some of said vias.