Method of forming isolated integrated injection logic gate

A method for the preparation of a semiconductor device which comprises the steps of:

• (1) providing a silicon substrate of P-type conductivity (20), and forming an ion-implanted buried N+ region (40) thereon;
• (2) forming an ion-implanted BP region (50);
• (3) forming an N-epitaxial layer (80) over said BN region (40) and said BP region (50);
• (4) implanting in said epitaxial region (80) deep N+ (DN) regions (60);
• (5) forming TN3 regions of p-type conductivity (85, 86) to form the field implant and the base implant of an upside down NPN transistor of an I2L device, the base link occurring in the TN3 region (85);
• (6) performing a I2L base etch to open the I2L base area and further etching to open bipolar base areas;
• (7) forming shallow P base region (87), depositing a polysilicon layer, performing a boron silicon implant, and forming an arsenic implant region;
• (8) etching selective areas of the polysilicon layer to form the emitters of a regular NPN transistor (111) and the collectors (89) of the upside down NPN transistor (110) of the I2L device in the arsenic implant regions of the polysilicon, and to form resistors (89′) from the boron implanted regions of the polysilicon;
• (9) forming implanted p+ type regions of conductivity PC1 and PC2 (90,91,92) to form the emitter/collector (90,91) of the LPNP transistor;
• (10) selectively etching and depositing metal to form silicide layers (177) overlying said p+ regions (90,91,92);
• and
• (11) forming a contact region and depositing a contact metal (170) on the surface of the structure overlying silicide layer (177) and p+ region (92).