US 6,232,163 B1 · Method of forming a semiconductor diode with depleted polysilicon gate structure

Abstract

A high voltage tolerant diode structure for mixed-voltage, and mixed signal and analog/digital applications. The preferred silicon diode includes a polysilicon gate structure on at least one dielectric film layer on a semiconductor (silicon) layer or body. A well or an implanted area is formed in a bulk semiconductor substrate or in a surface silicon layer on an SOI wafer. Voltage applied to the polysilicon gate film, electrically depletes it, reducing voltage stress across the dielectric film. An intrinsic polysilicon film may be counter-doped, implanted with a low doped implantation, implanted with a low doped source/drain implant, or with a low doped MOSFET LDD or extension implant. Alternatively, a block mask may be formed over the gate structure when defining the depleted-polysilicon gate silicon diode to form low series resistance diode implants, preventing over-doping the film. Optionally, a hybrid photoresist method may be used to form higher doped edge implants in the silicon to reduce diode series resistance without a block mask.

Claims10

Dependent claims

A method of making a semiconductor diode, comprising:

a) forming two isolation areas in a semiconductor substrate;
b) forming a gate dielectric layer on said substrate between said two isolation areas;
c) forming a gate layer on said gate dielectric layer, said gate layer including a first region of a first conductivity type and a second region of a second conductivity type;
d) forming first and second conduction regions in said substrate on either side of said gate layer;
and
e) lightly doping or counter-doping at least one of said first and second conduction regions such that an effective thickness of a depletion region in at least one of said substrate and said gate layer adjacent said gate dielectric layer increases with increasing electrical stress.

3 more elements

A method of forming a semiconductor diode, comprising the steps of:

a) forming trenches isolation in a surface of a semiconductor substrate;
b) forming a gate dielectric layer on said surface;
c) forming a gate on said dielectric layer between a pair of said trenches;
d) implanting a first dopant type into a first portion of said gate and into said surface between one trench isolation of said pair of trenches and said first portion;
and
e) implanting a second dopant type into a second portion of said gate and into said surface between the other trench isolation of said pair of trenches and said second portion,
wherein said implanting steps d) and e) are performed so that a dopant concentration of at least one of said first portion and said second portion of said gate is lower than a dopant concentration of at least one of said surface between said one trench isolation and said first portion and said surface between the other trench isolation and said second portion, the dopant concentrations being selected so as to cause a depletion layer to form which increases an effective thickness of said gate dielectric layer by an amount which improves electrical stress resistance of said diode.

4 more elements

Dependencies are inferred from the claim text.

Method of forming a semiconductor diode with depleted polysilicon gate structure

Life of this patent

Method of forming a semiconductor diode with depleted polysilicon gate structure

Life of this patent

Abstract

Claims10