Metal-gate non-volatile memory cell
OwnerYueh Yale Mainventor
Life of this patent
Estimating the term…
Abstract
In producing a metal-gate non-volatile memory cell, a layer of oxide is formed over a silicon substrate. A floating gate is then formed over the oxide. Source and drain regions are then formed in the silicon substrate such that at least one of the edges of the floating gate is aligned with its corresponding edge of one of the source and drain regions. A high temperature anneal cycle is then carried out to remove the defects in the source and drain regions. A composite layer of either Oxide-Nitride-Oxide-Polysilicon (ONOP) coupling dielectric or Oxide-Polysilicon (OP) coupling dielectric is then formed over the floating gate. Finally, a control gate made from metal is formed over the composite layer of ONOP or OP coupling dielectric.
Claims25
At least two non-volatile memory cells, each cell comprising:
- a source region and a drain region in a body substrate, said source and drain regions being separated by a channel region;
- a floating gate over but insulated from said channel region, wherein at least one of the edges of said floating gate is aligned with and used to define the corresponding edge of one of said source and drain regions;
- and
- a control gate from metal over but insulated from said floating gate,
- wherein the control gate extends over at least a portion of the floating gate of each of the at least two memory cells.
At least two dual-bit flash EEPROM cell structures, each cell structure comprising:
- a body region of one conductivity type;
- a first drain region and a second drain region formed in said body region, said drain regions being of a second conductivity type opposite said one conductivity type;
- a first stacked floating gate and control gate and a second stacked floating gate and control gate over said body region between said first drain region and said second drain region, said first and second stacked floating gate and control gate being spaced apart;
- a select gate extending over said body region between said first and second stacked floating gate and control gate;
- a first bit line contacting said first drain region;
- a second bit line contacting said second drain region;
- and
- a word line contacting said select gate, said word line being oriented generally perpendicular to said first bit line and said second bit line,
- wherein said word line and select gate are from metal, and said select gate further extends over at least a portion of each of the first and second stacked floating gate and control gate of each of the at least two memory cell structures.
An array of non-volatile memory cells in a body region, comprising:
- a plurality of floating gates over but insulated from said body region, said floating gates being arranged along a plurality of lines running in a first direction across said array;
- a plurality of continuous buried bitlines in said body region between said lines of floating gates, whereby the portions of said buried bitlines adjacent to said floating gates form source and drain regions of said memory cells, and at least one of the edges of said floating gates is aligned with and used to define the corresponding edge of one of said source and drain regions;
- and
- a plurality of control lines from metal running over but insulated from said floating gates, said plurality of control lines running in a direction other than said first direction, whereby portions of each control line running directly over said memory cells form control gates of said memory cells.
Dependencies are inferred from the claim text.