Method for analyzing probe yield sensitivities to IC design
AssigneeTexas Instruments Incorporated
InventorsNick Atchison, Ron Ross
Life of this patent
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Abstract
A method for predicting yield limits of semiconductor wafers in a factory, including the steps of generating a wafer probe test pareto, determining a histogram of the distribution from a selected group from the wafer probe test pareto, extracting parametric data from a database from the histogram, screening the parametric data for values of the parametric data outside of a predetermined range, determining if an average value of the screened parametric data shows a sensitivity to variations in the parametric data, determining specification limits of the screened parametric data, and using the specification limits to form an operating window to show the sensitivity.
Claims1
A method for predicting yield limits of semiconductor wafers in a factory, comprising the steps of:
- generating a wafer probe test pareto;
- determininig a histogram of the distribution from a selected group from the wafer probe test pareto;
- extracting parametric data from a database from said histogram;
- screening the parametric data for values of the parametric data outside of a predetermined range;
- determining if an average value of said screened parametric data shows a sensitivity to variations in said parametric data;
- determining specification limits of said screened parametric data;
- and
- using said specification limits to form an operating window to show said sensitivity.
Dependencies are inferred from the claim text.