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US 6,208,547 B1Granted
Memory circuit/logic circuit integrated device capable of reducing term of works
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTsukasa Ooishi
Life of this patent
Estimating the term…
Abstract
A memory circuit is connected to a logic circuit in a flip chip structure. The memory circuit is electrically connected with the logic circuit through an interface layer provided over a plurality of chips. The capacity of the memory connected to the logic circuit can be readily changed by simply changing the pattern of the interface, thereby reducing the term for developing a memory circuit/logic circuit integrated device.
Claims20
A memory circuit/logic circuit integrated device comprising:
- a logic circuit chip formed on a first major surface of a first semiconductor substrate, said logic circuit chip including a plurality of first input/output pads for electrically interfacing with the exterior of said logic circuit chip;
- a memory chip separated from a second semiconductor substrate having a plurality of memory circuits separably spaced on a second major surface, said memory chip including
- at least one said memory circuit,
- an insulator layer provided on the surface of said memory chip, and
- an interface wiring layer provided under said insulator layer and capable of being provided in common for a plurality of said memory circuits, said interface wiring layer having a plurality of second input/output pads each provided on a position corresponding to an opening part of said insulator layer for electrically interfacing with the exterior of said memory chip;
- and
- a plurality of connect members connecting said plurality of first input/output pads to corresponding said second input/output pads with said first major surface of said logic circuit chip faced to said second major surface of said memory chip.
4 more elements
A memory circuit/logic circuit integrated device comprising:
- a logic circuit chip formed on a first major surface of a first semiconductor substrate, said logic circuit chip including a plurality of first input/output pads for electrically interfacing with the exterior of said logic circuit chip;
- a memory chip separated from a second semiconductor substrate having a plurality of memory circuits separably spaced on a second major surface, said memory chip including
- at least two said memory circuit,
- an insulator layer provided on the surface of said memory chip, and
- an interface wiring layer provided under said insulator layer in common for said at least two memory circuits, said interface wiring layer having
- a plurality of wiring parts connecting respective input/output nodes of said memory circuits, and
- a plurality of second input/output pads each provided on a position corresponding to an opening part of said insulator layer for electrically interfacing with the exterior of said memory chip;
- and
- a plurality of connect members connecting said plurality of first input/output pads to corresponding said second input/output pads respectively with said first major surface of said logic circuit chip faced to said second major surface of said memory chip.
6 more elements
Dependencies are inferred from the claim text.