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US 6,208,494 B1Granted
Semiconductor integrated circuit device including electrostatic protection circuit accommodating drive by plurality of power supplies and effectively removing various types of surge
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsToru Nakura, Kimio Ueda
Life of this patent
Estimating the term…
Abstract
According to a structure in which each transistor of an output buffer transistor group of a gate array structure is electrically isolated, each body potential is set independent Also, a diode-connected transistor is provided between power supplies. An element not used in the output buffer transistor group can be connected without short-circuiting power supply lines between independent power supply lines to form an electrostatic protection circuit that is efficient in layout.
Claims19
A semiconductor integrated circuit device formed on a semiconductor substrate, comprising:
- a plurality of input/output terminals through which a signal is input/output with respect to an external source;
- first and second power supply lines to supply a first power supply potential;
- third and fourth power supply lines to supply a second power supply potential lower than said first power supply potential;
- a first transistor group formed on a main surface of said semiconductor substrate, and receiving power supply potential from said first and third power supply lines, said first transistor group including
- a plurality of transistors forming an internal circuit that carries out a predetermined process according to a signal applied to said input/output terminals to output a corresponding data signal;
- a second transistor group including a plurality of transistors formed on a main surface of said semiconductor substrate, receiving power supply potential from said second and fourth power supply lines, each transistor having the same transistor size, said second transistor group including
- a first transistor subgroup forming an output buffer provided between the input/output terminal from which said data signal is output out of said input/output terminals and said internal circuit, and that applies a buffer process on said data signal,
- a second transistor subgroup forming a first protection circuit protecting said output buffer and said internal circuit from a surge generated between said input/output terminal and any of said second and fourth power supply lines, and
- a third transistor subgroup forming a second protection circuit provided between said first power supply line and said second power supply line, and between said third power supply line and said fourth power supply line, to protect said internal circuit from a surge generated between said input/output terminal and any of said first and third power supply lines.
6 more elements
A semiconductor integrated circuit device formed on a semiconductor substrate, comprising:
- a plurality of input/output terminals through which a signal is input/output with respect to an external source;
- first and second power supply lines for applying a first power supply potential;
- third and fourth power supply lines for applying a second power supply potential lower than said first power supply potential;
- a first transistor group formed on a main surface of said semiconductor substrate, and receiving power supply potential from said first and third power supply lines, said first transistor group including
- a plurality of transistors forming an internal circuit that carries out a predetermined process according to a signal applied to said input/output terminals to output a corresponding data signal, each transistor having the same size;
- a second transistor group including a plurality of transistors formed on a main surface of said semiconductor substrate, receiving power supply potential from said second and fourth power supply lines, each transistor having the same transistor size, said second transistor group including
- a first transistor subgroup forming an output buffer provided between the input/output terminal from which said data signal is output out of said input/output terminals and said internal circuit, and that applies a buffer process on said data signal,
- a second transistor subgroup forming a first protection circuit protecting said output buffer and said internal circuit from a surge generated between said input/output terminal and any of said second and fourth power supply lines, and
- a third transistor subgroup forming a second protection circuit provided between said first power supply line and said second power supply line, and between said third power supply line and said fourth power supply line to protect said internal circuit from a surge generated between said input/output terminal and any of said first and third power supply lines.
6 more elements
A semiconductor integrated circuit device formed on a semiconductor substrate, comprising:
- a first power supply line to supply a first power supply potential;
- a second power supply line to supply a second power supply potential lower than said first power supply potential;
- a plurality of input/output terminals through which a signal is input/output with respect to an external source;
- an electrostatic protection circuit removing a surge generated between said input/output terminals and any of said first and second power supply lines;
- and
- a transistor group formed on a main surface of said semiconductor substrate, receiving a power supply potential from said first and second power supply lines, said transistor group including
- a first plurality of transistor subgroups provided for said input/output terminals, a source/drain resistance of the transistor in each of said transistor subgroups being different from that in every other transistor subgroup,
- each of said transistor subgroups having
- a first transistor belonging to said electrostatic protection circuit and coupled between said first power supply line and a corresponding input/output terminal out of said input/output terminals, and
- a second transistor belonging to said electrostatic protection circuit and coupled between said second power supply line and said corresponding input/output terminal.
7 more elements
Dependencies are inferred from the claim text.