Semiconductor integrated circuit
AssigneeNEC Corporation
InventorTadashi Haruki
Life of this patent
Estimating the term…
Abstract
In a semiconductor integrated circuit including a plurality of standard cells which are arranged in an array direction to constitute a logic circuit and which are supplied with a clock signal, each of the standard cells has a first side and a second side opposite to each other and extending in the array direction, and a clock signal terminal for receiving the clock signal is provided on only the first side of each of the standard cells. In each of the standard cells, there exists no internal interconnection which is used to supply the clock signal within the standard cell and which reaches the second side of the standard cell.
Claims10
A semiconductor integrated circuit including a plurality of standard cells which are arranged in an array direction to constitute a logic circuit and which are supplied with a clock signal, each of said standard cells having a first side and a second side opposite to each other and extending in said array direction, each of said standard cells having on only said first side a clock signal terminal for receiving said clock signal, each of said standard cells having no internal interconnection which is used to supply the clock signal within the standard cell and which reaches said second side of the standard cell.
A semiconductor integrated circuit including a plurality of standard cells which are arranged in an array direction to constitute a logic circuit and which are supplied with a clock signal, each of said standard cells having a first side and a second side opposite to each other and extending in said array direction, each of said standard cells having on only said first side a clock signal terminal for receiving the clock signal, said second side of each of said standard cells having no terminal for receiving said clock signal.
A semiconductor integrated circuit including a plurality of standard cells which are arranged in an array direction to constitute a logic circuit and which are supplied with a clock signal, each of said standard cells having a first side and a second side opposite to each other and extending in said array direction, each of said standard cells having on only said first side a clock signal terminal connected to a clock signal interconnection for receiving the clock signal, each of said standard cells having no internal interconnection extending between said second side and a contact which connects an internal interconnection connected to said clock signal terminal and for supplying said clock signal within the standard cell, an interconnection of another level.
Dependencies are inferred from the claim text.