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US 6,207,979 B1Granted
Gate array and manufacturing method of semiconductor integrated circuit using gate array
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorShigenobu Maeda
Life of this patent
Estimating the term…
Abstract
In a gate array, a gate length is measured by dividing gate electrodes into groups according to their materials to distinguish between those groups. The shape of a contact pad portion (5) of a gate electrode (4) differs according to the groups. A difference described here appears as shape such as cutouts (6a-6c) or projections (6d-6f), which is distinguishable by a scanning electron microscope, for example.
Claims20
A gate array comprising:
- a plurality of first rows formed by arranging a plurality of first MIS transistors on a semiconductor substrate;
- and
- a plurality of second rows formed by arranging a plurality of second MIS transistors on said semiconductor substrate,
- wherein there is a difference in shape of a structural member, distinguishable by appearances, between said first and second rows, wherein each of said plurality of first rows contains an identical first structure member and each of said plurality of second rows contains an identical second structural member.
1 more element
A gate array comprising:
- a plurality of first rows formed by arranging a plurality of first MIS transistors on a semiconductor substrate;
- and
- a plurality of second rows formed by arranging a plurality of second MIS transistors on said semiconductor substrate,
- wherein there is a difference in shape of a structural member, distinguishable by appearances, between said first and second rows;
- wherein said structural member is a contact pad portion of a gate electrode, and
- wherein said contact pad portion of said gate electrode includes a protruding part;
- said protruding part in said plurality of first rows is arranged in a first direction;
- and
- said protruding part in said second plurality of rows is arranged in a second direction different from said first direction.
6 more elements
A gate array comprising:
- a plurality of first rows formed by arranging a plurality of first MIS transistors on a semiconductor substrate;
- and
- a plurality of second rows formed by arranging a plurality of second MIS transistors on said semiconductor substrate,
- wherein there is a difference in shape of a structural member, distinguishable by appearances, between said first and second rows, and wherein
- said structural member includes a field oxide film.
2 more elements
A gate array comprising:
- a plurality of first MIS transistors of a first conductivity type formed on a semiconductor substrate;
- and
- a plurality of second MIS transistors of a second conductivity type formed on said semiconductor substrate,
- wherein there is a difference in shape of a structural member, distinguishable by appearance, between said first and second MIS transistors, wherein each of said plurality of first MIS trasistors contain an identical first structural member and each of said plurality of second MIS transistors contains an identical second structural member.
1 more element
A gate array comparing:
- a plurality of first MIS transistors of a first conductivity type formed on a semiconductor substrate;
- and
- a plurality of second MIS transistors of a second conductivity type formed on said semiconductor substrate,
- wherein there is a difference in shape of a structural member, distinguishable by appearances, between said first and second MIS transistors,
- wherein said structural member is a contact pad portion of a gate electrode, and
- wherein said contact pad portion of said gate electrode includes a protruding part,
- said protruding part of said plurality of first MIS transistors is arranged in a first direction;
- and
- said protruding part of said second plurality of MIS transistors is arranged in a second direction different from said first direction.
6 more elements
A gate array comprising:
- a plurality of first MIS transistors of a first conductivity type formed on a semiconductor substrate;
- and
- a plurality of second MIS transistor of a second conductivity type formed on said semiconductor substrate,
- wherein there is a difference in shape of a structural member, distinguishable by appearances, between said first and second MIS transistors, and wherein
- said structural member includes a field oxide film.
2 more elements
A gate array comprising:
- a plurality of first rows formed by arranging a plurality of first MIS transistors on a semiconductor substrate;
- and
- a plurality of second rows formed by arranging a plurality of second MIS transistors on said semiconductor substrate,
- wherein there is a difference in shape of a structural member, distinguishable by appearances, between said first and second rows, and
- a contact pad portion of a gate electrode is provided with only one contact.
2 more elements
A gate array comprising:
- a plurality of first MIS transistors of a first conductivity type formed on a semiconductor substrate;
- and
- a plurality of second MIS transistors of a second conductivity type formed on said semiconductor substrate,
- wherein there is a difference in shape of a structural member, distinguishable by appearances, between said first and second MIS transistors, and
- a contact pad portion of a gate electrode is provided with only one contact.
2 more elements
Dependencies are inferred from the claim text.