Method for forming an integrated circuit
AssigneeChartered Semiconductor Manufacturing Ltd.
InventorFeng Gao
Life of this patent
Estimating the term…
Abstract
In one embodiment, a first dielectric layer (16) is formed overlying a semiconductor substrate (4). A portion of the first dielectric layer (16) is then etched using a patterned masking layer (18). The patterned masking layer (18) is removed and an intermediate polishing layer (20) is formed overlying the first dielectric layer (16). A second dielectric layer (22) is formed overlying the intermediate polishing layer (20), and the second dielectric layer (22) is polished to expose a portion of the intermediate polishing layer (20), and to determine a polishing rate for the second dielectric layer (22). The polishing rate for the second dielectric layer (22) is then used to calculate a polishing time for the first dielectric layer (16), and the first dielectric layer (16) is polished for the calculated time.
Claims26
A method for forming an integrated circuit comprising the steps of:
- providing a substrate;
- forming a patterned trench mask overlying the substrate;
- etching the substrate to form a trench in the substrate;
- forming a first dielectric layer overlying the substrate, wherein the first dielectric layer overlies the patterned trench mask and lies within the trench;
- forming a patterned masking layer overlying the first dielectric layer;
- using the patterned masking layer to etch a portion of the first dielectric layer;
- removing the patterned masking layer;
- forming an intermediate polishing layer overlying the first dielectric layer, after the patterned masking layer has been removed;
- forming a second dielectric layer overlying the intermediate polishing layer;
- polishing the second dielectric layer to expose a portion of the intermediate polishing layer, and to determine a polish rate for the second dielectric layer;
- using the polish rate for the second dielectric layer to determine a polish time for the first dielectric layer;
- and
- polishing the first dielectric layer for the polish time to expose the patterned trench mask.
A method for forming an integrated circuit comprising the steps of:
- providing a substrate;
- forming a patterned trench mask overlying the substrate;
- etching the substrate to form a trench in the substrate;
- forming a first dielectric layer overlying the substrate, wherein the first dielectric layer overlies the patterned trench mask and lies within the trench;
- forming an intermediate polishing layer overlying the first dielectric layer;
- forming a second dielectric layer overlying the intermediate polishing layer;
- polishing the second dielectric layer to form an exposed portion of the intermediate polishing layer, and to determine a polish rate for the second dielectric layer;
- using the polish rate for the second dielectric layer to determine a polish time for the first dielectric layer;
- and
- polishing the first dielectric layer for the polish time to expose the patterned trench mask.
A method for forming an integrated circuit comprising the steps of:
- providing a substrate;
- forming a patterned layer overlying the substrate;
- forming a first layer of material overlying the patterned layer;
- forming a second layer of material overlying the first layer of material, wherein the second layer of material is different from the first layer of material;
- forming a third layer of material overlying the second layer of material, wherein the third layer of material is different from the second layer of material;
- polishing the third layer of material to form an exposed portion of the second layer of material, and to determine a polish rate for the third layer of material;
- using the polishing rate for the third layer of material to determine a polishing condition for the first layer of material;
- and
- polishing the first layer of material using the polishing condition to form a planarized surface.
Dependencies are inferred from the claim text.