US 6,207,532 B1Granted

STI process for improving isolation for deep sub-micron application

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsChrong Jung Lin, Shui-Hung Chen, Jiaw-Ren Shih

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Abstract

A new method is provided for the creation of a Shallow Trench Isolation region. A layer of pad oxide is deposited on the surface of a substrate; a layer of nitride is deposited over the layer of pad oxide. The layers of pad oxide and nitride are patterned and etched over the region where the STI is to be formed, a trench is etched in the silicon for the STI region. A layer of TEOS, that serves as a buffer spacer oxide, is deposited over the surface of the layer of nitride thereby including the inside of the created trench. The layer of TEOS is etched removing the TEOS from the surface of the nitride and from the bottom of the trench but leaving a layer of TEOS in place along the sidewalls of the trench. The bottom of the trench is next etched after which the TEOS spacer buffer is removed from the sidewalls of the trench. The sidewalls of the trench now have a non-linear profile. A layer of TEOS is deposited and polished leaving the trench filled with TEOS and at the same time removing the nitride from the surface of the pad oxide. N-well and P-well implants are performed after which N+ and P+ implants are performed around the periphery of the STI trench.

Claims21

Dependent claims

A method of forming a narrow deep trench isolation on a semiconductor substrate, comprising the steps of:

providing a semiconductor substrate;
forming a pad layer over the surface of said substrate;
forming a barrier layer over the surface of said pad layer;
patterning said barrier layer and said pad layer forming an opening;
etching said substrate through said opening forming a first trench in said substrate said first trench having sidewalls and a bottom, said first trench having sloping sidewalls whereby a surface area of a cross section of said first trench in a plane that is parallel with the surface of said substrate decreases in size the further said cross section is removed from the surface of said substrate;
growing a layer of first oxide over the surface of said patterned barrier layer and said patterned pad layer thereby including inside surfaces of said first trench;
forming buffer oxide spacers over said sidewalls of said first trench;
etching said substrate on said bottom of said first trench forming a second trench, said second trench having sloping sidewalls whereby a surface area of a cross section of said second trench in a plane that is parallel with the surface of said substrate decreases in size the further said cross section is removed from the surface of said substrate;
removing said buffer oxide spacers from said sidewalls of said first trench;
depositing a second layer of oxide over the surface of said patterned barrier layer thereby including said first trench and said second trench;
polishing using CMP said second layer of oxide thereby removing said second layer of oxide from above the surface of said patterned barrier layer thereby furthermore removing said patterned barrier layer from above said pad layer;
performing N-well and P-well implants in the surface of said substrate said N-well and P-well implants to be aligned with and adjacent to and on opposite sides of said first and second trench;
and
performing N+ and P+ implants around the periphery of said first trench.

11 more elements

A method of forming a narrow deep trench isolation on a semiconductor substrate, comprising the steps of:

providing a semiconductor substrate;
forming a layer of pad oxide over the surface of said substrate to a thickness of between 20 and 500 Angstrom;
forming a silicon nitride layer over the surface of said layer of pad oxide to a thickness between about 200 and 5000 Angstrom;
patterning said silicon nitride layer and said pad oxide layer forming an opening said opening to overlay and align with the region on the surface of said substrate where said narrow deep trench isolation is to be formed;
etching said substrate through said opening forming a first trench in said substrate said first trench having sidewalls and a bottom said first trench having a depth from the surface of said substrate of between about 1.0 and 3.0 um;
depositing a first layer of TEOS to a thickness between about 1000 and 3000 Angstrom over the surface of said patterned silicon nitride layer thereby including the inside surfaces of said first trench;
forming TEOS spacers over said sidewalls of said first trench to a thickness of between about 300 and 600 Angstrom said TEOS spacers to be formed by etching said deposited layer of TEOS;
etching said substrate on said bottom of said first trench forming a second trench said second trench having a depth from the surface of said substrate of between about 4.0 and 10.0 um;
removing said TEOS spacers from said sidewalls of said first trench;
depositing a second layer of TEOS oxide over the surface of said patterned silicon nitride layer to a thickness between about 1000 and 3000 Angstrom thereby including said first trench and said second trench;
polishing said second layer of TEOS oxide using CMP thereby removing said second layer of TEOS oxide from above the surface of said patterned silicon nitride layer thereby furthermore removing said patterned silicon nitride layer from above said pad oxide layer;
performing N-well and P-well implants in the surface of said substrate said N-well and P-well implants to be aligned with and adjacent to and on opposite sides of said first and second trench;
and
performing N+ and P+ implants around the periphery of said first trench wherein said performing N+ implants is implanting arsenic or phosphorous at a dose of between about 2.0E15 and 1.0E16 ions/cm3 and an energy of between about 20 and 70 KeV wherein furthermore said performing P+ implants is implanting boron or indium at a dose of between about 1.0E15 and 1.0E16 ions/cm3 and an energy of between about 50 and 90 KeV.

11 more elements

Dependencies are inferred from the claim text.