Dual gate FET and process

A method of fabricating a dual gate structure comprising:

• (a) providing a structure having a first oxide layer formed over a silicon substrate, wherein said first oxide layer contains a first gate region embedded therein and said silicon substrate contains two regions comprising a bottom nitride layer and a top oxide layer formed between said first gate region;
• (b) bonding an exposed surface of said oxide layer to a handling wafer;
• (c) polishing away a portion of said silicon substrate stopping at said bottom nitride layer;
• (d) removing said nitride layer from said polished silicon substrate;
• (e) growing oxide regions in said polished silicon substrate provided in step (d);
• (f) forming a protective layer of polysilicon over said polished silicon substrate provided in step (e);
• (g) opening a hole through at least a portion of said protective layer, said oxide region, said top oxide layer and said first oxide layer extending down to said first gate region;
• (h) depositing an outer layer of polysilicon over said protective layer and in said hole;
• (i) patterning the polysilicon layer and protective layer and developing the pattern so as to provide a second gate region directly over the underlying first gate region;
• (j) implanting source and drain regions in said silicon substrate adjacent to said second gate region;
• and
• (k) annealing the structure provided in step (j).