Method of fabricating flash erasable programmable read only memory

A method of fabricating a flash erasable programmable read only memory, the method comprising the steps of:

• providing a substrate having an isolation structure, the isolation structure comprising a shallow trench isolation;
• forming a tunnel oxide layer and a patterned floating gate layer on the substrate;
• performing a first-type ion implantation step to form a first doped region in the substrate;
• forming a first oxide layer over the substrate;
• forming a nitride/oxide layer over the first oxide layer;
• forming a control gate layer over the nitride/oxide layer;
• patterning the first gate layer, the nitride/oxide layer, the first oxide layer, and the floating gate layer until the substrate is exposed;
• performing an ion implantation with the isolation structure as a mask;
• forming spacers on sidewalls of the control gate layer, the nitride/oxide layer, the first oxide layer, the floating gate layer, and the tunnel oxide layer;
• and
• performing a self-aligned silicide step to form silicide layers over the control gate, the common source region, and the drain region.

A method of fabricating a flash erasable programmable read only memory, the method comprising the steps of:

• providing a substrate having an isolation structure;
• forming a tunnel oxide layer and a patterned floating gate layer on the substrate;
• performing a first-type ion implantation step to form a first doped region in the substrate;
• forming a first oxide layer over the substrate;
• forming a nitride/oxide layer over the first oxide layer;
• forming a control gate layer over the nitride/oxide layer;
• patterning the first gate layer, the nitride/oxide layer, the first oxide layer, and the floating gate layer until the substrate is exposed;
• performing an ion implantation with the isolation structure as a mask;
• forming spacers on sidewalls of the control gate layer, the nitride/oxide layer, the first oxide layer, the floating gate layer, and the tunnel oxide layer;
• and
• performing a self-aligned silicide step to form silicide layers over the control gate, the common source region, and the drain region, wherein the material of the silicide layers comprises CoSi2.