DRAM chip fabrication method

Abstract

An improved method for forming a DRAM chip is disclosed. According to this method, a memory cell gate is deposited in a memory cell array area of the DRAM chip. The memory cell gate overlies a first channel area of a substrate. A peripheral gate is deposited in a peripheral area of the DRAM chip. The peripheral gate overlies a second channel area of the substrate. A first dopant is implanted with a first concentration in a first plurality of source and drain regions of the substrate lying predominantly outside the first and second channel areas of the substrate. A sidewall is then formed adjacent to the peripheral gate. Simultaneously, an insulating layer is formed over the memory cell array area of the DRAM chip. A second dopant is implanted with a second concentration in a second plurality of source and drain regions of the substrate within the peripheral area of the DRAM chip. The implant of the second dopant is blocked by the sidewall and the insulating layer. In one embodiment, the first and second dopants are the same, and the dopant concentration in the second plurality of regions is greater than the dopant concentration in the first plurality of regions. This method allows the formation of more heavily doped source and drain regions in the peripheral area of the DRAM chip while keeping the heavily doped regions separated from the channel regions. This reduces diffusion into the channel regions and allows a smaller design rule to be used.

Dependencies are inferred from the claim text.