Conformity of ultra-thin nitride deposition for DRAM capacitor

A method for fabricating a DRAM cell, the method comprising:

• providing a substrate;
• depositing a blanket first dielectric layer over the substrate;
• forming a first photoresist layer over said first dielectric layer, wherein said first photoresist layer is defined and etched to form a contact opening in the first dielectric layer;
• forming a first conductive layer to fill said contact opening, and performing an etching process to remove a portion of said first conductive layer to form a node contact;
• depositing a second conductive layer over said first dielectric layer and the node contact;
• forming a second photoresist layer over said second conductive layer, wherein said second photoresist layer is defined and etched to form a storage node as an upper electrode of a capacitor;
• forming a hemispherical silicon grain (HSG) over and on a sidewall of said second conductive layer;
• treating said hemispherical silicon grain (HSG) by plasma;
• depositing a conformal second dielectric layer over said hemispherical silicon grain (HSG) and said first dielectric layer after treating plasma;
• and
• forming a blanket third conductive layer over said substrate to serve as the upper electrode of the capacitor.

A method for fabricating a DRAM cell, the method comprising:

• providing a silicon substrate on which a transistor is formed;
• depositing a blanket inter-poly dielectric layer (IPD) over the silicon substrate;
• forming a first photoresist layer over said inter-poly dielectric layer, wherein said first photoresist layer is defined and etched to form a contact opening in said inter-poly dielectric layer (IPD);
• forming a metal conductive layer to fill said contact opening, and performing an etching process to remove a portion of said metal conductive layer to form a node contact;
• depositing a first doped polysilicon layer over said first inter-poly dielectric layer and the node contact;
• forming a second photoresist layer over said first doped polysilicon layer, wherein said second photoresist layer is defined and etched to form a storage node as an upper electrode of a capacitor;
• forming a hemispherical silicon grain (HSG) over and on a sidewall of said first doped polysilicon layer;
• treating said hemispherical silicon grain (HSG) by rapid thermal nitration (RTN);
• depositing a conformal silicon nitride layer over said hemispherical silicon grain (HSG) and said inter-poly dielectric layer after rapid thermal nitration (RTN);
• and
• forming a blanket second doped polysilicon layer over said silicon substrate to serve as the upper electrode of the capacitor.

A method for fabricating a DRAM cell, the method comprising:

• providing a silicon substrate on which a transistor is formed;
• depositing a blanket inter-poly dielectric layer (IPD) over the silicon substrate;
• forming a first photoresist layer over said inter-poly dielectric layer, wherein said first photoresist layer is defined and etched to form a contact opening in said inter-poly dielectric layer;
• forming a metal conductive layer to fill said contact opening, and performing an etching process to remove a portion of said metal conductive layer to form a node contact;
• depositing a first doped polysilicon layer over said first inter-polysilicon layer and the node contact;
• forming a second photoresist layer over said first doped polysilicon layer, wherein said second photoresist layer is defined and etched to form a storage node as an upper electrode of a capacitor;
• forming a hemispherical silicon grain (HSG) over and on a sidewall of said first doped polysilicon layer;
• treating said hemispherical silicon grain layer by plasma;
• depositing a conformal silicon nitride layer over said hemispherical silicon grain (HSG) and said inter-poly dielectric layer after treating plasma;
• and
• forming a blanket second doped polysilicon over said silicon substrate to serve as the upper electrode of the capacitor.