Method for preventing silicon substrate loss in fabricating semiconductor device

A method for eliminating leakage current in a semiconductor device by preventing silicon loss in a memory cell region of a substrate during fabricating said semiconductor device, said method comprising:

• forming a first gate structure on a periphery circuit region of said substrate, and a first structure together with a second structure on said first area of said substrate, said semiconductor device being a dynamic random access memory (DRAM);
• forming a dielectric layer on said first gate structure, said first structure, said second structure, and said exposed substrate;
• etching a first portion of said dielectric layer to remain a second portion of said dielectric layer;
• forming a photoresist pattern on said dielectric layer over periphery circuit region of said substrate;
• etching said exposed second portion of said dielectric layer using said photoresist pattern as a mask to form spacers of said first gate structure, wherein said spacers and said gate structure constitute a gate electrode;
• forming a source region and a drain region in said substrate, said gate electrode, said source region, and said drain region constituting a first transistor;
• removing said photoresist pattern;
• and
• forming a second transistor, a capacitor, and a control line in said memory cell region of said substrate by using said first structure and said second structure.

A method for eliminating leakage current in a semiconductor device by preventing silicon loss in a memory cell region of a substrate during fabricating said semiconductor device, said method comprising:

• forming a first gate structure on a periphery circuit region of said substrate, and a first structure together with a second structure on said first area of said substrate, said semiconductor device being a dynamic random access memory (DRAM);
• forming a dielectric layer on said first gate structure, said first structure, said second structure, and said exposed substrate;
• etching a first portion of said dielectric layer to remain a second portion of said dielectric layer, a thickness of said second portion of said dielectric layer being of a thickness about more than 200-1000 angstroms;
• forming a photoresist pattern on said dielectric layer over said periphery circuit region of said substrate;
• etching said exposed second portion of said dielectric layer using said photoresist pattern as a mask to form spacers of said first gate structure, wherein said spacers and said gate structure constituting a gate electrode;
• forming a source region and a drain region in said substrate, said gate electrode, said source region, and said drain region constituting a first transistor;
• removing said photoresist pattern;
• and
• forming a second transistor, a capacitor, and a control line in said memory cell region of said substrate by using said first structure and said second structure, charges stored in said capacitor being controlled by said second transistor, said control line, and said first transistor.