Modified poly-buffered isolation

A semiconductor device comprising:

• a semiconductor substrate;
• an oxide layer at least partially covering said substrate;
• a polysilicon layer partially covering said oxide layer;
• a first silicon nitride layer at least partially covering said polysilicon layer;
• a second silicon nitride layer at least partially covering said first silicon nitride layer, said first silicon nitride layer having a higher quality than said second silicon nitride layer, said second silicon nitride layer being formed by a chemical vapor deposition technique;
• and
• a field isolation oxide region at least partially covering said oxide layer and having a substantially reduced bird's beak structure disposed between said oxide layer and said polysilicon layer.

A semiconductor integrated circuit structure, said structure comprising:

• a semiconductor substrate having a top surface;
• an oxide layer partially overlying said top surface;
• a polysilicon layer partially overlying said oxide layer;
• a first silicon nitride layer overlying said polysilicon layer;
• and
• a second silicon nitride layer overlying said first silicon nitride layer, said first silicon nitride layer having a higher quality than said second silicon nitride layer,
• wherein said second silicon nitride layer, said first silicon nitride layer, and said polysilicon layer define a mask, said mask comprising exposed regions of said oxide layer.