ESD protection scheme

An integrated circuit device comprising:

• an integrated circuit pad;
• an internal integrated circuit conductively coupled to said integrated circuit pad so as to define a primary electrical path from said integrated circuit pad to said internal integrated circuit;
• and
• an ESD protection circuit conductively coupled to said integrated circuit pad so as to define a secondary electrical path from said integrated circuit pad to said ESD protection circuit, said ESD protection circuit comprising a semiconductor structure arranged to define
• a doped silicon substrate;
• a drain region formed in said silicon substrate, wherein said drain region is conductively coupled to said integrated circuit pad via said secondary electrical path,
• a source region formed in said silicon substrate, wherein said source region is conductively coupled to a relatively low electrical potential,
• an electrically insulating region formed in said silicon substrate between said drain region and said source region, and
• a gate structure conductively coupled to a relatively low electrical potential, wherein
• said gate structure is arranged such that, upon application of a relatively high electrical potential to said integrated circuit pad, gate-induced drain leakage current flows in said silicon substrate, and
• said gate structure and said electrically insulating region are arranged to define an active gate region limited to extend from said drain region to said electrically insulating region, such that said gate-induced drain leakage current tends to follow a path through said silicon substrate substantially offset from said active gate region.

An integrated circuit device comprising:

• an integrated circuit pad;
• an internal integrated circuit conductively coupled to said integrated circuit pad so as to define a primary electrical path from said integrated circuit pad to said internal integrated circuit;
• and
• an ESD protection circuit conductively coupled to said integrated circuit pad so as to define a secondary electrical path from said integrated circuit pad to said ESD protection circuit, said ESD protection circuit comprising a semiconductor structure arranged to define
• a doped silicon substrate having an upper surface and a substantially parallel lower surface;
• a drain region formed in said silicon substrate, wherein said drain region is conductively coupled to said integrated circuit pad via said secondary electrical path,
• a source region formed in said silicon substrate, wherein said source region is conductively coupled to a relatively low electrical potential,
• an electrically insulating region formed in said silicon substrate between said drain region and said source region, wherein said drain region and said source region extend a first predetermined distance into said silicon substrate from said upper surface of said silicon substrate, wherein said electrically insulating region extends a second predetermined distance into said silicon substrate from said upper surface of said silicon substrate, and wherein said second predetermined distance is at least as great as said first predetermined distance, and
• a gate structure formed on said upper surface of said silicon substrate and conductively coupled to a relatively low electrical potential, wherein
• said gate structure is arranged to define an incipient inversion layer in said drain region, wherein said incipient inversion layer is defined upon application of a relatively high electrical potential to said integrated circuit pad,
• said gate structure is arranged to overlap a portion of said drain region such that, upon application of said relatively high electrical potential to said integrated circuit pad, gate-induced drain leakage current flows in said silicon substrate, and
• said gate structure and said electrically insulating region are arranged to define an active gate region limited to extend in the vicinity of said upper surface of said silicon substrate from said drain region to said electrically insulating region,
• wherein said drain region, said source region, and said silicon substrate form a junction transistor having a characteristic breakdown voltage above which breakdown voltage breakdown current flows in said silicon substrate between said source region and said drain region, wherein said gate structure and said silicon substrate are arranged such that said gate-induced drain leakage current reduces said characteristic breakdown voltage, and wherein the size and location of said electrically insulating region formed in said silicon substrate are such that said breakdown current tends to follow a path substantially offset from said active gate region.

An ESD protection circuit conductively coupled to an integrated circuit pad so as to define an electrical path from the integrated circuit pad to said ESD protection circuit, said ESD protection circuit comprising a semiconductor structure arranged to define:

• a doped silicon substrate;
• a drain region formed in said silicon substrate, wherein said drain region is conductively coupled to said integrated circuit pad via said secondary electrical path;
• a source region formed in said silicon substrate, wherein said source region is conductively coupled to a relatively low electrical potential;
• an electrically insulating region formed in said silicon substrate between said drain region and said source region;
• and
• a gate structure conductively coupled to a relatively low electrical potential, wherein
• said gate structure is arranged to define an incipient inversion layer in said drain region, wherein said incipient inversion layer is defined upon application of a relatively high electrical potential to said integrated circuit pad, and
• said gate structure and said electrically insulating region are arranged to define an active gate region limited to extend from said drain region to said electrically insulating region.

An ESD protection circuit conductively coupled to said integrated circuit pad so as to define a secondary electrical path from an integrated circuit pad to said ESD protection circuit, said ESD protection circuit comprising a semiconductor structure arranged to define:

• a doped silicon substrate;
• a drain region formed in said silicon substrate, wherein said drain region is conductively coupled to said integrated circuit pad via said secondary electrical path;
• a source region formed in said silicon substrate, wherein said source region is conductively coupled to a relatively low electrical potential;
• an electrically insulating region formed in said silicon substrate between said drain region and said source region;
• and
• a gate structure conductively coupled to a relatively low electrical potential, wherein
• said gate structure is arranged such that, upon application of a relatively high electrical potential to said integrated circuit pad, gate-induced drain leakage current flows in said silicon substrate, and
• said gate structure and said electrically insulating region are arranged to define an active gate region limited to extend from said drain region to said electrically insulating region, such that said gate-induced drain leakage current tends to follow a path through said silicon substrate substantially offset from said active gate region.

A semiconductor structure comprising:

• a doped silicon substrate;
• a drain region formed in said silicon substrate;
• a source region formed in said silicon substrate;
• an electrically insulating region formed in said silicon substrate between said drain region and said source region;
• and
• a gate structure arranged to define
• an incipient inversion layer in said drain region, wherein said incipient inversion layer is defined upon application of a relatively high electrical potential to said drain region and upon application of a relatively low electrical potential to said gate structure, and, in combination with said electrically insulating region,
• an active gate region limited to extend from said drain region to said electrically insulating region.

A semiconductor structure comprising:

• a doped silicon substrate;
• a drain region formed in said silicon substrate;
• a source region formed in said silicon substrate;
• an electrically insulating region formed in said silicon substrate between said drain region and said source region;
• and
• a gate structure arranged to
• overlap a portion of said drain region such that, upon application of a relatively high electrical potential to said drain region and upon application of a relatively low electrical potential to said gate structure, gate-induced drain leakage current flows in said silicon substrate, and, in combination with said electrically insulating region,
• define an active gate region limited to extend from said drain region to said electrically insulating region, such that said gate-induced drain leakage current tends to follow a path through said silicon substrate substantially offset from said active gate region.