Pillar transistor incorporating a body contact

A transistor comprising:

• a butted junction between a P+ region and an N+ region;
• a silicon pillar in electrical contact with and straddling the butted junction, the silicon pillar having a top portion and a side;
• a doped region formed at the top portion of the silicon pillar;
• a gate dielectric formed on the side of the silicon pillar;
• and
• a gate conductor formed on the gate dielectric.

A field effect transistor comprising:

• a semiconductor substrate;
• an N+ region and a P+ region formed in the semiconductor substrate, the N+ region adjacent to the P+ region and forming a butted junction;
• an isolation region surrounding the N+ region and the P+ region;
• a single crystal silicon pillar straddling the butted junction such that the single crystal silicon pillar is in electrical contact with the N+ region and the P+ region, the silicon pillar having a gate side proximate the N+ region and a top portion;
• a N+ implant formed in the top portion of the silicon pillar
• a gate dielectric formed on the gate side of the silicon pillar;
• and
• a gate conductor formed adjacent to the dielectric;
• a dielectric layer covering the N+ region, the P+ region, the isolation region and the silicon pillar;
• a gate contact stud formed in the dielectric layer, the gate contact stud in electrical contact with the gate conductor;
• a source contact stud formed in the dielectric layer, the source contact stud in electrical contact with the N+ region;
• a drain contact stud formed in the dielectric layer, the drain contact stud in electrical contact with the top portion of the silicon pillar;
• and
• a body contact stud formed in the dielectric layer, the body contact stud in electrical contact with the P+ region.