US 6,204,530 B1 · Flash-type nonvolatile semiconductor memory devices for preventing overerasure

Abstract

A nonvolatile semiconductor memory device includes a p-type semiconductor substrate having a surface region, and bit lines formed as n-type first diffusion regions in the surface region, extending in a column direction. The bit lines define between them a plurality of separated, parallel channel regions, extending in a row direction. A plurality of conductive floating gates are formed over first portions of respective channel regions on a first insulating layer, and extend over portions of the first diffusion regions. A plurality of conductive control gates is formed to extend over the floating gates, and over second portions of the channel regions that are not covered by the floating gates. The control gates are separated from the floating gates and from the second portions by additional insulating layers. A common source line is formed by an elongated conductor extending in the column direction, over the control gates and insulated from them. A plurality of n-type second diffusion layers are formed in the surface region between successive second portions of the channel regions and connected to the common source line. These define an intermittent source line under the control gate layers. At the points of interruption, the second diffusion layers form selection transistors with the control gates, which are turned on or off depending on whether the corresponding cell is being read. When read, they prevent reading out any error data if the memory cell had been over-erased.

Drawings

Claims17

Dependent claims

A nonvolatile semiconductor memory device comprising:

a semiconductor substrate of a first conductivity type having a surface region;
a first diffusion region of a second conductivity type opposite to the first conductivity type, formed in said surface region to extend in a first direction;
a plurality of channel regions in said surface region, separated from one another and extending from an edge of said first diffusion region in a second direction generally perpendicular to the first direction;
a plurality of floating gate layers of conductive material, each floating gate layer formed over a first portion of a respective channel region on a first insulating layer and extending over a portion of said first diffusion region;
a plurality of control gate layers of conductive material formed to extend over said floating gate layers and over second portions of said channel regions not covered by said floating gate layers, and separated from said floating gate layers by a second insulating layer and from said second portions by a third insulating layer;
and
a plurality of second diffusion layers of the second conductivity type, formed in said surface region between neighboring ones of said second portions of said channel regions.

4 more elements

A nonvolatile semiconductor device comprising:

a semiconductor substrate of a first conductivity type having a surface region;
a pair of first diffusion regions of a second conductivity type opposite to the first conductivity type, formed in said surface region and extending in a first direction so as to be separated from and parallel to each other;
a plurality of channel regions in said surface region, defined between said first diffusion regions in a second direction generally perpendicular to the first direction, and separated from one another, each of said channel regions having a pair of first channel regions contiguous to said pair of said first diffusion regions and a second channel region therebetween;
pairs of floating gate layers of conductive material disposed over said first channel regions on a first insulating layer and over side portions of said first diffusion regions;
a plurality of control gate layers of conductive material each formed to extend in the second direction on a second insulating layer overlying a respective one of said pairs of said floating gate layers and on a third insulating layer overlying said second channel region therebetween;
a plurality of second diffusion regions of the second conductivity type, disposed in said surface region between neighboring ones of said second channel regions;
and
an elongated conductive layer disposed over said control gate layers on a fourth insulating layer and contacting said second diffusion regions.

5 more elements

Dependencies are inferred from the claim text.

Description4,870 words

Summary1,815 words

#1. Field of the Invention

#The present invention relates to nonvolatile semiconductor memory devices, and more particularly to flash-type electrically erasable programmable read only memory (EEPROM) devices with overerasure preventing structures.

#2. Description of the Related Art

Brief description of the drawings11 figures

#These and various other features and advantages of the present invention will be readily understood with reference to the following detailed description taken in conjunction with the accompanying drawings, in which:

#FIG. 1 illustrates an enlarged plan view of a portion of a virtual ground type flash EEPROM memory cell array according to the prior art;

#FIG. 2 illustrates a cross-sectional view taken along a line 2-2′ shown in FIG. 1;

Detailed description2,829 words

#Preferred embodiments of the present invention will be described with reference to FIGS. 4 to 14. It should be noticed that in the drawings, like reference number or symbol represents like element or part.

#FIG. 4 shows an enlarged plan view of a portion of an array of flash EEPROM memory cells according to one embodiment of the present invention. For the convenience of explanation, although four memory cells are illustrated, it is obvious to those skilled in the art that a multiplicity of memory cells are arranged in a matrix form of rows and columns on a semiconductor substrate. FIGS. 5A, 5B and 6 show enlarged cross-sectional views taken along lines 5A-5A′, 5B-5B′ and 6-6′ in FIG. 4, respectively. FIG. 7 shows a schematic equivalent circuit diagram of FIG. 4.

#Referring to FIGS. 4 through 6, a substrate 10 may be a p-well on a surface of an n-type semiconductor substrate, a p-well in an n-well on a surface of a p-type semiconductor substrate, or an appropriate region in a semiconductor substrate. As a person skilled in the art will appreciate, the conductivities of the various structures are interchangeable.

Facts

Application

09/374,545Filed 13 Aug 1999

Priority

KR 98-3285913 Aug 1998

Granted

20 Mar 2001

Term ended

13 Aug 2019

Estimated · how

20 years from earliest known nonprovisional domestic filing. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination. Patent term adjustment is unavailable; no adjustment was added.

Classification5 codes

H10B 69/00
Erasable-and-programmable rom [eprom] devices not provided for in groups h10b41/00 - h10b63/00
H10D 30/683
Having only two programming levels: programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
H10D 64/035
Of data-storage electrodes: comprising conductor-insulator-conductor-insulator-semiconductor structures
H10B
Electronic memory devices

Flash-type nonvolatile semiconductor memory devices for preventing overerasure

Life of this patent

Flash-type nonvolatile semiconductor memory devices for preventing overerasure

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims17

Description4,870 words

Drawings

Classification5 codes

Life of this patent

Description4,870 words