Method to prevent CMP overpolish
AssigneeVanguard International Semiconductor Corporation
InventorsRong-Wu Chien, Chia-Hui Wu, Honda Pai
Life of this patent
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Abstract
A process for avoiding dishing in a planarizing layer whose final thickness is reduced by Chem. Mech. Polishing, is described. The first step is to coat the surface to be planarized with a layer of a hard dielectric material, such as silicon nitride, prior to depositing the planarizing medium. After the latter has been reflowed, its thickness is reduced by means of CMP. While CMP is being applied, the etch rate is constantly sensed. When the etch front approaches the aforementioned hard layer a decrease in the etch rate is sensed and etching is terminated, thereby eliminating any dishing effects.
Claims20
A process for preventing overpolishing during CMP, comprising:
- providing means for measuring polishing rate during CMP;
- providing a dielectric layer having a upper surface;
- coating said upper surface with a polysilicon layer;
- patterning and etching the polysilicon layer thereby forming a step on the upper surface of the dielectric layer;
- coating said upper surface and said patterned polysilicon layer, including the step, with a layer of a hard dielectric material;
- depositing a planarizing layer on said layer of hard material;
- heating said planarizing layer to a temperature sufficient to cause reflow, thereby forming a planar top surface;
- by means of CMP, etching the planar top surface while measuring the polishing rate;
- and
- terminating CMP when said polishing rate is measured to have decreased by a preset amount.
A process to prevent overpolishing of an ILD layer during manufacture of an integrated circuit, comprising the sequential steps of:
- providing means for measuring polishing rate during CMP;
- providing a partially completed integrated circuit, including a silicon substrate, regions of field oxide, field effect transistors, spacers, and a first planarizing dielectric layer having an upper surface;
- etching a via hole through said first dielectric layer down to the level of the field effect transistors;
- filling the via hole with a suitable conductive plug;
- coating said upper surface with a polysilicon layer;
- etching the polysilicon layer to form a pattern that contacts said conductive plug, thereby forming a step on the upper surface of the dielectric layer;
- coating said upper surface, including the step and said polysilicon pattern, with a layer of a hard dielectric material;
- depositing an ILD layer on said layer of hard material;
- heating said ILD layer to a temperature sufficient to cause reflow, thereby forming a planar top surface;
- by means of CMP, etching the planar top surface while measuring the polishing rate;
- and
- terminating CMP when said polishing rate is measured to have decreased by a preset amount.
Dependencies are inferred from the claim text.