US 6,204,137 B1Granted

Method to form transistors and local interconnects using a silicon nitride dummy gate technique

AssigneeChartered Semiconductor Manufacturing Ltd.

InventorsKok Hin Teo, Feng Chen, Alex See, Lap Chan

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Abstract

A new method of forming MOS transistors has been achieved. A pad oxide layer is grown. A silicon nitride layer is deposited. Trenches are etched for planned STI. A trench liner is grown inside of the trenches. A trench oxide layer is deposited filling the trenches. The trench oxide layer is polished down to complete the STI. The same silicon nitride layer is patterned to form dummy gates. A gate liner layer is deposited. Ions are implanted to form lightly doped drain junctions. Sidewall spacers are formed adjacent to the dummy gate electrodes and the shallow trench isolations. Ions are implanted to form the drain and source junctions. An epitaxial silicon layer is grown overlying the source and drain junctions. A metal layer is deposited. The epitaxial silicon layer is converted into sulicide to form silicided source and drain contacts. An interlevel dielectric layer is deposited and polished down to the dummy gates. The dummy gates are etched away to form openings for the planned transistor gates. A gate oxide layer is deposited lining the transistor gate openings. A gate electrode layer is deposited to fill the transistor gate openings. The gate electrode layer is patterned to complete the transistor gates.

Claims20

Dependent claims

A method to form transistor gates in the manufacture of an integrated circuit device comprising:

depositing a silicon nitride layer overlying a semiconductor substrate;
patterning said silicon nitride layer and said semiconductor substrate to form trenches for planned shallow trench isolations;
depositing a trench oxide layer overlying said silicon nitride layer and filling said trenches;
polishing down said trench oxide layer to said silicon nitride layer to complete said shallow trench isolations;
thereafter patterning said silicon nitride layer to form dummy gates where said transistor gates are planned;
depositing an oxide liner layer overlying said dummy gates, said shallow trench isolations, and said semiconductor substrate;
implanting ions into said semiconductor substrate to form lightly doped drain junctions;
forming sidewall spacers adjacent to said dummy gates and said shallow trench isolations;
thereafter implanting ions into said semiconductor substrate to form source and drain junctions;
thereafter depositing an interlevel dielectric layer overlying said dummy gates, said shallow trench isolations, and said semiconductor substrate;
polishing down said interlevel dielectric layer to said dummy gates;
etching away said dummy gates to form openings for planned transistor gates;
depositing a gate oxide layer lining said openings for planned transistor gates;
depositing a gate electrode layer overlying said gate oxide layer and filling said openings for planned transistor gates;
and
patterning said gate electrode layer to complete said transistor gates and to complete the local interconnects for said transistors in the manufacture of the integrated circuit device.

13 more elements

A method to form transistor gates in the manufacture of an integrated circuit device comprising:

growing a pad oxide layer overlying a semiconductor substrate;
depositing a silicon nitride layer overlying said pad oxide layer;
patterning said silicon nitride layer, said pad oxide layer, and said semiconductor substrate to form trenches for planned shallow trench isolations;
depositing a trench oxide layer overlying said silicon nitride layer and filling said trenches;
polishing down said trench oxide layer to the top surface of said silicon nitride layer to complete said shallow trench isolations;
thereafter patterning said silicon nitride layer to form dummy gates where said transistor gates are planned;
depositing an oxide liner layer overlying said dummy gates, said shallow trench isolations, and said semiconductor substrate;
implanting ions into said semiconductor substrate to form lightly doped drain junctions;
forming sidewall spacers adjacent to said dummy gates and said shallow trench isolations;
thereafter implanting ions into said semiconductor substrate to form source and drain junctions;
thereafter depositing an interlevel dielectric layer overlying said dummy gates, said shallow trench Isolations, and said semiconductor substrate;
polishing down said interlevel dielectric layer to said dummy gates;
etching away said dummy gates to form openings for planned transistor gates;
depositing a gate oxide layer lining said openings for planned transistor gates;
depositing a gate electrode layer overlying said gate oxide layer and filling said openings for planned transistor gates;
and
patterning said gate electrode layer to complete said transistor gates and to complete the local interconnects for said transistors in the manufacture of the integrated circuit device.

14 more elements

A method to form transistor gates in the manufacture of an integrated circuit device comprising:

providing a semiconductor substrate;
growing a pad oxide layer overlying said semiconductor substrate;
depositing a silicon nitride layer overlying said pad oxide layer;
patterning said silicon nitride layer, said pad oxide layer, and said semiconductor substrate to form trenches for planned shallow trench isolations;
growing a trench liner oxide layer overlying said semiconductor substrate inside of said trenches;
depositing a trench oxide layer overlying said silicon nitride layer and filling said trenches;
polishing down said trench oxide layer to said silicon nitride layer to complete said shallow trench isolations;
thereafter patterning said silicon nitride layer to form dummy gates where transistor gates are planned;
depositing an oxide liner layer overlying said dummy gates, said shallow trench isolations, and said semiconductor substrate;
implanting ions into said semiconductor substrate to form lightly doped drain junctions;
forming sidewall spacers adjacent to said dummy gates and said shallow trench isolations;
thereafter implanting ions into said semiconductor substrate to form source and drain junctions;
selectively growing an epitaxial silicon layer overlying said source and drain junctions;
depositing a metal layer overlying said epitaxial silicon layer;
annealing said metal layer and said epitaxial silicon layer to convert said epitaxial silicon layer into salicide and to thereby form silicided source and drain contacts;
removing remaining said metal layer;
depositing an interlevel dielectric layer overlying said dummy gates, said shallow trench isolations, and said silicided source and drain contacts;
polishing down said interlevel dielectric layer to said dummy gates;
etching away said dummy gates to form openings for said planned transistor gates;
depositing a gate oxide layer lining said openings for said planned transistor gates;
depositing a gate electrode layer overlying said gate oxide layer and filling said openings for said planned transistor gates;
and
patterning said gate electrode layer to complete said transistor gates and to completed the local interconnects for said transistors in the manufacture of the integrated circuit device.

20 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/556,386Filed 24 Apr 2000
Granted: 20 Mar 2001
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10D 64/017
Manufacture or treatment: using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e.…
H10W 10/014
Of isolation regions comprising dielectric materials: using trench refilling with dielectric materials, e.g. shallow trench isolations
H10W 10/17
Isolation regions comprising dielectric materials: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
H10D
Inorganic electric semiconductor devices