Methods of forming nonvolatile integrated circuit memory devices having high capacitive coupling ratios

A method of forming a non-volatile memory device, comprising the steps of:

• forming a field oxide isolation region on inactive portions of a semiconductor substrate;
• forming a tunneling oxide layer on active portions of the semiconductor substrate;
• forming a first electrically conductive layer on the tunneling oxide layer;
• forming a floating gate electrode mask on the first electrically conductive layer, opposite the tunneling oxide layer;
• forming a second electrically conductive layer on sidewalls of the floating gate electrode mask and in electrical contact with the first electrically conductive layer;
• patterning the second electrically conductive layer to define a U-shape floating gate electrode comprising portions of the first and second electrically conductive layers;
• forming an electrically insulating layer on the U-shaped floating gate electrode and on the field oxide isolation region;
• etching back the electrically insulating layer to define a buried electrically insulating region on the field oxide isolation region and expose the floating gate electrode mask;
• removing the floating gate electrode mask;
• forming an interlayer insulating layer on the U-shaped floating gate electrode and on the buried electrically insulating region;
• and
• forming a control gate on the interlayer insulating layer, opposite the U-shaped floating gate electrode.

A method of forming an EEPROM memory device, comprising the steps of:

• forming a field oxide isolation region on inactive portions of a semiconductor substrate;
• forming a tunneling oxide layer having a thickness in a range between about 70 Å and 100 Å on active portions of the semiconductor substrate;
• depositing a first polysilicon layer having a thickness in a range between about 1000 Å and 3000 Å on the tunneling oxide layer;
• forming a floating gate electrode mask comprising silicon nitride on the first polysilicon layer, opposite the tunneling oxide layer;
• depositing a second polysilicon layer having a thickness in a range between about 1000 Å and 2000 Å on the first polysilicon layer and on sidewalls of the floating gate electrode mask;
• anisotropically etching the second polysilicon layer and the first polysilicon layer to expose the field oxide isolation region and define a U-shaped floating gate electrode;
• depositing an electrically insulating layer on the floating gate electrode mask and on the field oxide isolation region;
• etching back the electrically insulating layer to define a buried electrically insulating region on the field oxide isolation region and expose the floating gate electrode mask;
• removing the floating gate electrode mask to expose the U-shaped floating gate electrode;
• forming an interlayer insulating layer on the U-shaped floating gate electrode and on the buried electrically insulating region;
• and
• forming a control gate on the interlayer insulating layer, opposite the U-shaped floating gate electrode.