Method for bottom electrode of capacitor

Abstract

A method of fabricating a bottom electrode of a capacitor, in which a semiconductor substrate is provided wherein a transistor is formed thereon and the transistor contains a source/drain region. A dielectric layer having a contact hole is formed over the substrate wherein a portion of the source/drain region is exposed by the contact hole. A doped polysilicon layer is formed over the substrate. An insulating layer is formed on the doped polysilicon layer. An amorphous silicon layer is formed on the insulating layer. The amorphous silicon layer, the insulating layer and the doped polysilicon layer are defined to form a main structure of the bottom electrode. Amorphous silicon spacers are formed on sidewalls of the main structure. A hemispherical grained silicon layer is formed on the amorphous silicon layer and the amorphous silicon spacers.

Dependencies are inferred from the claim text.