US 6,204,117 B1Granted

Removal of silicon oxynitride on a capacitor electrode for selective hemispherical grain growth

AssigneeUnited Microelectronics Corp.

InventorsJung-Chao Chiou, Chuan-Fu Wang

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Abstract

A method of forming a capacitor for a dynamic random access memory (DRAM) cell using a selective hemispherical grain (s-HSG) structure after the removal of SiON by phosphoric acid (H3PO4) is disclosed. The method includes: Providing a semiconductor substrate having a semiconductor structure formed thereon; forming an interlayer dielectric layer over the semiconductor structure; patterning the interlayer dielectric layer; depositing an amorphous-silicon (a-Si) layer over the interlayer dielectric layer; depositing a SiON layer on the a-Si layer; patterning the SiON layer and the a-Si layer layer; removing the SiON layer by H3PO4 wet etching; forming a s-HSG silicon layer over the patterned a-Si layer; depositing a conformal interpoly dielectric layer along a surface of the resulting structure; and finally forming a polysilicon layer over the interpoly dielectric layer.

Claims23

Dependent claims

A method of forming a capacitor, comprising the steps of:

providing a semiconductor substrate having a semiconductor body formed thereon;
forming a first insulating layer above said substrate and overlaying said semiconductor body;
patterning said first insulating layer to define a contact hole for said capacitor;
depositing an amorphous silicon layer as a first conductive layer over said first insulating layer and filling up said contact hole;
forming a silicon oxynitride layer on said amorphous silicon layer to serve as photo bottom anti-reflective coating (BARC) and etching hard mask for capacitor patterns;
patterning said silicon oxynitride layer and said amorphous silicon layer to form a lower capacitor electrode;
removing said silicon oxynitride layer to expose the entire upper surface of said lower capacitor electrode, through a wet etching method utilizing phosphoric acid (H3PO4) solution at temperature about 150° C.;
forming a selective hemispherical gram (s-HSG) silicon layer as a second conductive layer over the entire exposed surface of said lower capacitor electrode;
forming a second insulating layer along a surface of the resulting structure and over said second conductive layer;
and
forming a third conductive layer over said second insulating layer serve as an upper capacitor electrode.

8 more elements

A method of forming a capacitor for a dynamic random access memory (DRAM) cell using a selective hemispherical grain (s-HSG) structure, said method comprising the steps of:

providing a semiconductor substrate having a semiconductor structure formed thereon;
forming an interlayer dielectric layer above said substrate and overlaying said semiconductor structure;
forming a first patterned photoresist film on said interlayer dielectric layer;
etching said interlayer dielectric layer by using said first patterned photoresist film as a mask, hence forming a contact hole and exposing a portion of an active area of said semiconductor structure;
stripping off said first patterned photoresist film;
depositing a first silicon layer over said interlayer dielectric layer and filling up said contact hole in said interlayer dielectric layer;
forming a silicon oxynitride layer on said first silicon layer to serve as photo bottom anti-reflective coating (BARC) and etching hard mask for capacitor patterns;
forming a second patterned photoresist film on said silicon oxynitride layer;
etching said silicon oxynitride layer and first silicon layer by using said second patterned photoresist film as a mask, hence forming a lower capacitor electrode and exposing a portion of the upper surface of said interlayer dielectric layer;
stripping off said second patterned photoresist film;
removing said silicon oxynitride layer and to expose the entire upper surface of said lower capacitor electrode through a wet etching method utilizing phosphoric acid (H3PO4) solution at temperature about 150° C.;
forming a selective hemispherical grain (s-HSG) silicon layer over the entire exposed surface of said lower capacitor electrode;
forming a conformal interpoly dielectric layer along a surface of the resulting structure and over said s-HSG silicon layer;
and
forming a second silicon layer over said conformal interpoly dielectric layer to serve as an upper capacitor electrode.

12 more elements

Dependencies are inferred from the claim text.