Back to results
US 6,204,115 B1Granted
Manufacture of high-density pillar memory cell arrangement
AssigneeStanford University
InventorHyun-Jin Cho
Life of this patent
Estimating the term…
Abstract
A fabrication process benefits high-density DRAM cells, including four-Gbit cells and beyond. In one embodiment, a poly-Si pillar transistor is formed on top of a trench capacitor with the top of the pillar transistor being directly connected to the bit line. To reduce the process steps, word line formation is achieved by a spacer etch process and a self-aligned process is used for formation of bit line contact using a CMP process. This embodiment reduces necessary layout area and provides improvements in overall device performance.
Claims23
A process of fabricating a memory cell including a capacitive structure, comprising:
- forming a pillar transistor over a semiconductor material with the pillar transistor including an amorphous silicon material, a non-conductive layer over the amorphous silicon material, and a first conductive layer around the pillar structure;
- forming a dielectric material over the pillar transistor;
- removing the dielectric material until the non-conductive layer is exposed;
- removing the non-conductive layer;
- and
- forming another conductive layer on pillar structure, wherein the capacitive structure is formed vertically in line with the pillar transistor and the underlying semiconductor material.
3 more elements
A process of fabricating a DRAM cell, comprising:
- forming a capacitor over a first semiconductor material;
- forming a second semiconductor material over the capacitor;
- forming a non-conductive layer over the second semiconductor material;
- forming a pillar structure over the capacitor;
- forming a conductive layer around the pillar structure and therein forming part of a pillar transistor;
- forming a dielectric material over the pillar transistor;
- removing the dielectric material until the non-conductive layer is exposed;
- removing the non-conductive layer;
- and
- forming a conductive layer on the pillar structure.
7 more elements
A process of fabricating a DRAM cell, comprising:
- forming a capacitor over a semiconductor material;
- forming an amorphous silicon material over the capacitor;
- forming a non-conductive SiN-based layer over the semiconductor material;
- forming a pillar structure, including the amorphous silicon material and the non-conductive SiN-based layer, over the capacitor via an etching process;
- forming a conductive layer around the pillar structure to form a pillar transistor including the conductive layer and the pillar structure;
- forming a dielectric material over the pillar transistor;
- removing the dielectric material, via CMP, until the non-conductive SiN-based layer is exposed;
- removing the non-conductive (SiN) layer and forming a conductive layer on the pillar structure.
5 more elements
A process of fabricating a DRAM cell, comprising:
- forming a conductive layer;
- forming a pillar structure, including a semiconductor material, over the conductive layer and including a nonconductive SiN-based layer over the semiconductor material;
- forming a word line around the pillar and therein forming a pillar transistor;
- forming a dielectric material over the pillar transistor;
- removing the dielectric material until non-conductive SiN-based layer is exposed;
- removing the non-conductive SiN-based layer;
- forming another conductive layer on the pillar transistor;
- forming a capacitor over the pillar transistor.
5 more elements
A process of fabricating a memory device, comprising:
- forming a capacitor over a semiconductor material;
- forming an amorphous silicon material over the capacitor;
- forming a non-conductive SiN-based layer over the amorphous silicon material;
- forming a pillar structure, including the amorphous silicon material and the non-conductive SiN-based layer, over the capacitor;
- conducting a recrystallization annealing of the pillar structure;
- forming a first dielectric material around the pillar structure;
- forming a conductive layer around the pillar structure via a spacer etching process;
- forming a second dielectric material over the pillar transistor;
- removing the second dielectric material, via CMP, until the non-conductive SiN-based layer is exposed;
- and
- removing the non-conductive (SiN) layer and forming a conductive layer on the pillar structure.
8 more elements
A process of fabricating a memory device, comprising:
- forming a conductive layer;
- forming an amorphous silicon material over the conductive layer;
- forming a non-conductive SiN-based layer over the amorphous silicon material;
- forming a pillar structure, including the amorphous silicon material and the non-conductive SiN-based layer;
- conducting a recrystallization annealing of the pillar structure;
- forming a dielectric material around the pillar structure;
- forming a conductive layer around the pillar structure via a spacer etching process;
- forming a dielectric material over the pillar transistor;
- removing the dielectric material, via CMP, until the non-conductive SiN-based layer is exposed;
- removing the non-conductive (SiN) layer and forming a conductive layer on the pillar structure;
- forming a capacitor over the pillar structure.
8 more elements
A process of fabricating a transistor, comprising:
- forming an amorphous silicon material over a non-conducting amorphous material;
- forming a non-conductive SiN-based layer over the amorphous silicon material;
- forming a pillar structure, including the amorphous silicon material and the non-conductive SiN-based layer;
- conducting a recrystallization annealing of the pillar structure;
- forming a dielectric material around the pillar structure;
- forming a conductive layer around the pillar structure via a spacer etching process;
- forming a dielectric material over the pillar transistor;
- removing the dielectric material, via CMP, until the non-conductive SiN-based layer is exposed;
- removing the non-conductive (SiN) layer and forming a conductive layer on the pillar structure.
6 more elements
Dependencies are inferred from the claim text.