US 6,204,113 B1Granted

Method of forming data storage capacitors in dynamic random access memory cells

AssigneeUnited Microelectronics Corp.

InventorGary Hong

Life of this patent

Estimating the term…

Loading patent…

Abstract

A method of forming data storage capacitors in DRAM cells, which data storage capacitors each have an increased surface area for the charge storage plates of the capacitors in order to increase the capacitance. The individual method allows ULSI (Ultra Large Scale Integration) DRAMs, although reduced in circuit element size, to be formed with data storage capacitors having a sufficiently large capacitance to reliably retain electric charges. In this method, a double-trench structure is formed in at least two overlaying conductive layers serving as a bottom plate of the data storage capacitor. A dielectric layer is then formed over the bottom plate, and subsequently, another conductive layer serving as a top plate of the data storage capacitor is formed over the dielectric layer. In this semiconductor structure, the double-trench structure in the data storage capacitor increases the surface area of the bottom plate, thus proportionally increasing the capacitance of the data storage capacitor.

Claims19

Dependent claims

A method of forming a data storage capacitor in a DRAM cell, comprising the steps of:

(a) providing a semiconductor substrate having at least one MOS transistor including a pair of source/drain regions formed thereon, and a first insulating layer formed over the said MOS transistor, with said first insulating layer having an opening to expose one of said source/drain regions;
(b) forming a first conductive layer over said first insulating layer and completely filling said opening;
(c) forming an insulating hump directly on said first conductive layer and centered over said opening;
(d) forming a second conductive layer on the outer surface of the substrate to cover said first conductive layer and said insulating hump;
(e) on the second conductive layer, forming only one pair of insulating material spacers which are disposed on and adjacent to sidewalls of a protruding part of said second conductive layer that covers said insulating hump;
(f) using said spacers and said insulating hump as an etching mask, anisotropically etching exposed portions of said second conductive layer and an underlying portion of said first conductive layer to remove all parts of said first and second conductive layers which are outside of said spacers and to form only one pair of trenches extending into said first conductive layer to a given depth inside a region surrounded by the spacer;
(g) removing said spacers and said insulating hump;
(h) forming a dielectric layer on the outer surface of said substrate to cover remaining parts of said first and second conductive layers;
and
(i) forming a third conductive layer over said dielectric layer, whereby remaining parts of said first and second conductive layers, said dielectric layer, and said third conductive layer in combination constitute a data storage capacitor of a DRAM cell.

7 more elements

A method of forming a data storage capacitor in a DRAM cell, comprising the steps of:

(a) providing a semiconductor substrate having formed thereon at least one MOS transistor including a pair of source/drain regions, and a first oxide layer formed over said MOS transistor, with said first oxide layer having an opening to expose one of said source/drain regions;
(b) forming a first conductive polysilicon layer over said first oxide layer and completely filling said opening;
(c) forming a second oxide layer directly on said first conductive polysilicon layer over said opening;
(d) selectively etching the surface of the substrate to remove selected parts of said second oxide layer to form an oxide hump directly on said first conductive polysilicon layer and centered over said opening;
(e) forming a second conductive polysilicon layer over said first conductive polysilicon layer and said oxide hump;
(f) on the second conductive layer, forming only one pair of insulating material spacers which are disposed on and adjacent to sidewalls of a protruding part of said second conductive polysilicon layer that covers said oxide hump;
(g) using said spacers and said oxide hump as an etching mask, anisotropically etching exposed portions of said second conductive polysilicon layer and an underlying portion of said first conductive polysilicon layer to remove all parts of said first and second conductive polysilicon layers which are outside of said spacers and to form only one pair of trenches extending into said first conductive polysilicon layer within a region surrounded by the spacers and between the spacers and the oxide hump;
(h) removing said spacers and said oxide hump;
(i) forming a dielectric layer on the outer surface of the substrate to cover remaining parts of said first and second conductive polysilicon layers;
and
(j) forming a third conductive polysilicon layer over said dielectric layer, whereby remaining parts of said first and second conductive polysilicon layers, said dielectric layer, and said third conductive polysilicon layer in combination constitute a data storage capacitor of a DRAM cell.

8 more elements

A method of forming a data storage capacitor in a DRAM cell, comprising the steps of:

(a) providing a semiconductor substrate having at least one MOS transistor including a pair of source/drain regions formed thereon, and a first insulating layer formed over said MOS transistor, with said first insulating layer having an opening to expose one of said source/drain regions;
(b) forming a first conductive layer over said first insulating layer and filling said opening;
(c) forming an insulating hump, consisting of only a single layer of material, directly on said first conductive layer and centered over said opening;
(d) forming a second conductive layer on the outer surface of the substrate to cover said first conductive layer and said insulating hump;
(e) on the second conductive layer, forming only one pair of insulating material spacers which are disposed on and adjacent to sidewalls of a protruding part of said second conductive layer that covers said insulating hump;
(f) using said spacers and said insulating hump as an etching mask, anisotropically etching exposed portions of said second conductive layer and an underlying portion of said first conductive layer to remove all parts of said first and second conductive layers which are outside of said spacers and to form a pair of trenches extending into said first conductive layer to a given depth inside a region surrounded by the spacers, wherein sidewalls of the insulating hump are exposed;
(g) removing said spacers and said insulating hump;
(h) forming a dielectric layer on the outer surface of said substrate to cover remaining parts of said first and second conductive layers;
and
(i) forming a third conductive layer over said dielectric layer, whereby remaining parts of said first and second conductive layers, said dielectric layer, and said third conductive layer in combination constitute a data storage capacitor of a DRAM cell.

7 more elements

A method of forming a data storage capacitor in a DRAM cell, comprising the steps of:

(a) providing a semiconductor substrate having formed thereon at least one MOS transistor including a pair of source/drain regions, and a first oxide layer formed over said MOS transistor, with said first oxide layer having an opening to expose one of said source/drain regions;
(b) forming a first conductive polysilicon layer over said first oxide layer and filling said opening;
(c) forming a second oxide layer directly on said first conductive polysilicon layer over said opening;
(d) selectively etching the surface of the substrate to remove selected parts of said second oxide layer to form an oxide hump directly on said first conductive polysilicon layer and centered over said opening, with the oxide hump consisting of only a single layer of oxide;
(e) forming a second conductive polysilicon layer over said first conductive polysilicon layer and said oxide hump;
(f) on the second conductive layer, forming only one pair of insulating material spacers which are disposed on and adjacent to sidewalls of a protruding part of said second conductive polysilicon layer that covers said oxide hump;
(g) using said spacers and said oxide hump as an etching mask, anisotropically etching exposed portions of said second conductive polysilicon layer and an underlying portion of said first conductive polysilicon layer to remove all parts of said first and second conductive polysilicon layers which are outside of said spacers and to form a pair of trenches extending into said first conductive polysilicon layer within a region surrounded by the spacers and between the spacers and the oxide hump, and exposing sidewalls of the hump;
(h) removing said spacer and said oxide hump;
(i) forming a dielectric layer on the outer surface of the substrate to cover remaining parts of said first and second conductive polysilicon layers;
and
(j) forming a third conductive polysilicon layer over said dielectric layer, whereby remaining parts of said first and second conductive polysilicon layers, said dielectric layer, and said third conductive polysilicon layer in combination constitute a data storage capacitor of a DRAM cell.

8 more elements

Dependencies are inferred from the claim text.