Process to make complementary silicide metal gates for CMOS technology
AssigneeIntel Corporation
InventorsGang Bai, Brian S. Doyle
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Abstract
The present invention provides a method of forming first and second transistor devices. A first region of silicide is formed over a first portion of a gate dielectric that overlies a first well region in a semiconductor substrate. A second region of silicide is formed over a second portion of the gate dielectric. The second portion of the gate dielectric overlies a second well region in the semiconductor substrate. First and second doped junction regions are formed in the first and second well regions respectively.
Claims20
A method of forming a first and second transistor devices, the method comprising:
- a. forming first region of silicide over a first portion of a gate dielectric that overlies a first well region in a semiconductor substrate;
- b. forming a second region of silicide, over a second portion of said gate dielectric that overlies a second well region in said semiconductor substrate;
- and
- c. forming first and second doped regions, in said first and second well regions, respectively.
A method of forming a complementary semiconductor device, the method comprising:
- forming an isolation between a first and a second metal oxide semiconductor field effect transistors (MOSFET);
- forming a first metal layer on top of a gate of said first MOSFET;
- forming a second metal layer on top of a gate of said second MOSFET;
- forming a first region of silicide by causing said first metal layer to react with underlying polysilicon material included in said gate of said first MOSFET;
- and
- forming a second region of silicide by causing said second metal layer to react with underlying polysilicon material included in said gate of said second MOSFET.
Dependencies are inferred from the claim text.