US 6,204,096 B1 · Method for reducing critical dimension of dual damascene process using spin-on-glass process

Abstract

A method for forming wiring structures in integrated circuit devices is disclosed. The method, in one embodiment, firstly providing a substrate is carried out. Then an interlayer dielectric layer is formed over the substrate. Sequentially an etching stop layer is formed and wherein the etching stop layer is patterned. Thus formation of a dielectric layer over the etching stop is achieved. Also photoresist mask is formed and defined. Therefore an opening for a via is initially formed in a second insulative layer above a first insulative layer with an etching stop layer therein. Consequentially removing the photoresist mask and then depositing a first conductive metal layer are all carried out. Again, photoresist mask is formed and defined. The next step is removing excess parts of the conductive metal. Sequentially the step is depositing a second conductive metal layer. Finally the surface of integrated circuit device is planarized herein.

Claims12

Dependent claims

A method for controlling critical dimension of an integrated circuit device having multiple level conductive structures comprising the steps of:

providing a substrate;
forming an interlayer dielectric layer over said substrate;
forming an etching stop layer and wherein said etching stop layer being patterned;
forming a dielectric layer over said etching stop;
patterning said dielectric layer to define as wiring line;
depositing a first conductive metal layer;
patterning said first conductive layer over said etching stop and then over said interlayer dielectric layer to define as wiring line;
removing excess parts of said conductive metal;
depositing a second conductive metal layer;
and
planarizing said surface of integrated circuit device herein.

8 more elements

A method of forming a conductive wiring and a via on a substrate, comprising the steps of:

providing a substrate for semiconductor device;
forming a first insulative layer on said substrate;
forming an etching stop layer on said first insulative layer;
forming a second insulative layer on said etch stop layer;
forming an opening in said second insulative layer at a first location where said via is desired, said opening penetrating through said second insulative layer substantially up into said etching stop layer;
forming a trench in said second insulative layer at a second location where said wiring is desired while simultaneously extending said opening through said etching stop layer and through said first insulative layer wherein said trench is wider than and entirely inclusive of said opening;
depositing a first conductive metal in said opening and in said trench so that said first conductive metal completely fills said opening and said trench, said trench forming a conductive wiring, said opening in said etching stop layer and said first insulative layer forming a conductive via, said conductive via providing electrical connection between a conductive wiring and said substrate;
forming a photoresist mask on said first conductive metal layer;
defining wiring line onto surface of said first conductive metal as a pattern layer;
removing said photoresist mask;
removing said first conductive metal;
depositing simultaneously a second conductive metal in said opening and in said trench so that said conductive material completely fills said opening and said trench, said trench forming a conductive wiring, said opening in said etching stop layer and said first insulative layer forming a conductive via, said conductive via providing electrical connection between a conductive wiring and said substrate;
and
planarizing surface of said second conductive metal.

11 more elements

Dependencies are inferred from the claim text.

Method for reducing critical dimension of dual damascene process using spin-on-glass process

Life of this patent

Method for reducing critical dimension of dual damascene process using spin-on-glass process

Life of this patent

Abstract

Claims12