Method for ashing
AssigneeOki Electric Industry Co., Ltd.
InventorToshiro Mitsuhashi
Life of this patent
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Abstract
A method for ashing a resist pattern covered by a hardened layer caused by an ion implantation process previously conducted including a first step for conducting an ashing process at a first temperature e.g. 129° C. or less at which no popping phenomenon happens, for removing the hardened layer, and a second step for conducting an ashing process at a second temperature e.g. 150° C. at which the ashing rate is high, for entirely removing the remaining resist pattern, and apparatus employable for the method for ashing a resist pattern covered by a hardened layer including a mechanism for moving up and down a semiconductor wafer to regulate the temperature of the semiconductor wafer and including a shutter which intervenes between the semiconductor wafer and a heater.
Claims6
A method for ashing a wafer having a resist pattern covered by a hardened layer caused by an ion implantation process previously conducted, said method comprising:
- conducting a first ashing process as a first temperature at which no popping phenomenon occurs and at which said hardened layer is removed, and
- conducting a second ashing process as a second temperature at which an ashing rate thereof is higher than that of said first ashing process and at which said resist pattern is removed;
- wherein the first and second ashing processes take place in a same chamber while the wafer is continually maintained in on a same wafer support.
A method for ashing a resist pattern covered by a hardened layer caused by an ion implantation process previously conducted, said method comprising:
- conducting a first ashing process at a first temperature at which no popping phenomenon occurs and at which said hardened layer is removed;
- conducting a second ashing process at a second temperature at which an ashing rate thereof is higher than that of said first ashing process and at which said resist pattern is removed;
- supporting a semiconductor water on a horizontal wafer support contained within a reaction chamber, the horizontal wafer support moveable in a vertical direction, and the semiconductor wafer containing the resist pattern covered by the hardened layer;
- maintaining a stage continued within the reaction chamber at a given temperature;
- positioning the horizontal water at a first position relative to the stage, wherein said first ashing process is conducted while said horizontal water support is at the first position;
- positioning the horizontal wafer at a second position relative to the stage, said second position of the horizontal wafer support being closer to the stage than said first position, wherein said second process is conducted while said horizontal wafer support is at second position.
A method for ashing a resist pattern covered by a hardened layer caused by an ion implantation process previously conducted, said method comprising:
- conducting a first ashing process at a first temperature at which no popping phenomenon occurs and at which said hardened layer is removed;
- conducting a second ashing process at a second temperature at which an ashing rate thereof is higher than that of said first ashing process and at which said resist pattern is removed;
- supporting a semiconductor wafer on a horizontal wafer support contained within a reaction chamber, the reaction chamber further containing a heating mechanism, and the semiconductor wafer containing the resist pattern covered by the hardened layer;
- positioning a thermal shutter between the heating mechanism and the horizontal wafer support during said first ashing process;
- and
- removing the thermal shutter from between the heating mechanism and the horizontal wafer support during said second ashing process.
Dependencies are inferred from the claim text.