Non-volatile semiconductor integrated memory device

A semiconductor integrated memory device comprising a plurality of memory cell blocks, which are arranged in the form of a matrix and each of which comprises:

• a memory cell column having a plurality of memory cells connected in series, each memory cell comprising a memory capacitor, which has at least a first electrode, a second electrode facing said first electrode, and a ferroelectric thin-film sandwiched between said first and second electrodes, and a control transistor connected to between said first and second electrodes;
• a reference capacitor having at least a third electrode, which electrically connected to said first electrode of said memory capacitor arranged at one end of said memory cell column, a fourth electrode facing said third electrode, and a dielectric thin-film sandwiched between said third and fourth electrodes;
• and
• a read transistor having a gate electrode electrically connected to said first and third electrodes.

A semiconductor integrated memory device comprising a plurality of memory cell blocks, which are arranged in the form of a matrix and each of which comprises:

• a NAND type memory cell column comprising a plurality of selecting MOS transistors connected in series, and a plurality of memory capacitors of dielectric films, each of which is sandwiched between a storage electrode connected to a common main electrode of each of said selecting MOS transistors, and a plate electrode facing said storage electrode;
• a reference capacitor electrically connected to a main electrode of said selecting transistor arranged at one end of said memory cell column;
• and
• a read transistor having a gate electrode electrically connected to a connection part between a main electrode of said selecting MOS transistor and a main electrode of said reference capacitor.