US 6,191,975 B1 · Non-volatile NAND type semiconductor memory device with stacked gate memory cells and a stacked gate select transistor

Abstract

In the field of EEPROM, memory cell structures and operation methods have been required which are suitable for ultrahigh-integration and high-reliability EEPROMS with no danger of erroneous writing. To meet this requirement, in this invention, the gate of each of select gate cells located on the source line side and the bit line side of a NAND type memory cell array is formed of two layers of a charge storage layer and a control gate layer as with memory cells. The select gate cells are formed at the same time in the same process as memory cells. The ion implantation conditions for the cell channels are set so as to optimize the memory cell channel boost ratio. The optimization of the cutoff characteristic required of the select gate cells is performed by injection of charges into the charge storage layers of the select gate cells without owing to ion implantation. The memory and select gate cells are formed into the same shape. The charge storage layer is formed to self-align to an isolation trench.

Claims12

Dependent claims

A non-volatile semiconductor memory device comprising:

a memory cell array including NAND cells, each of the NAND cells having a plurality of memory cells and at least one of a first select gate cell and a second select gate cell, the plurality of memory cells being connected in series to form a NAND string, the first select gate cell being connected between a bit line and the memory cell nearest to the bit line, the second select gate cell being connected between a source line and the memory cell nearest to the source line, and each of the memory cells having a charge storage layer and a control gate layer, wherein
each of the first select gate cell and the second select gate cell has a control gate layer and a charge storage layer each of which is of substantially the same dimension as that of the memory cells, and
writing data into the first and second select gate cells is performed prior to writing data into the memory cells.

A non-volatile semiconductor memory device comprising:

a memory cell array including NAND cells, each of the NAND memory cells having a plurality of memory cells and at least one of a first select gate cell and a second select gate cell, the plurality of memory cells being connected in series to form a NAND string, the first select gate cell being connected between a bit line and the memory cell nearest to the bit line, the second select gate cell being connected between a source line and the memory cell nearest to the source line, and each of the memory cells having a charge storage layer and a control gate layer, wherein
each of the first select gate cell and the second select gate cell has a control gate layer and a charge storage layer,
the memory cells and the first and second select gate cells are formed in each of a plurality of device regions defined by device isolation regions formed by filling isolation trenches extending along a direction of a semiconductor substrate with an insulating material,
the charge storage layer of each of the memory cells and the first and second select gate cells is formed above the device region to self-align to the device region with a first gate insulating film interposed therebetween,
the control gate layer of each of the memory cells and the first and second select gate cells is formed above the charge storage layer with a second gate insulating film interposed therebetween, the second gate insulating film covering a top and part of the sidewall of the charge storage layer, the charge storage layer is self-aligned to the isolation trenches, and has a lower portion contiguous to the device isolation region and an upper portion that is opposite to the control gate layer with the second gate insulating film interposed therebetween, and a height of the lower portion of the charge storage layer is substantially the same for the memory cells and the first and second select gate cells.

2 more elements

A non-volatile semiconductor memory device comprising:

a memory cell array including NAND memory cells, each of the NAND memory cells having a plurality of memory cells and at least one of a first select gate cell and a second select gate cell, the plurality of memory cells being connected in series to form a NAND string, the first select gate cell being connected between a bit line and the memory cell nearest to the bit line, the second select gate cell being connected between a source line and the memory cell nearest to the source line, and each of the memory cells having a charge storage layer and a control gate layer, wherein
each of the first select gate cell and the second select gate cell has a control gate layer and a charge storage layer,
a plurality of transfer transistors are provided, each of which is connected in parallel with a corresponding respective one of the memory cells and the first and second select gate cells, and
a threshold voltage of the transfer transistors is substantially equal to that of at least one of the first and second select gate cells.

1 more element

Dependencies are inferred from the claim text.

Non-volatile NAND type semiconductor memory device with stacked gate memory cells and a stacked gate select transistor

Life of this patent

Non-volatile NAND type semiconductor memory device with stacked gate memory cells and a stacked gate select transistor

Life of this patent

Abstract

Claims12