US 6,191,602 B1 · Wafer acceptance testing method and structure of a test key used in the method

Abstract

A wafer acceptance testing (WAT) method with a test key is provided. The test key structure includes a testing structure on a substrate. An inter-layer-dielectric layer covers over the substrate to isolate the testing structure. A grounded metal layer is located on the inter-layer dielectric layer. An interconnecting structure is located on the grounded metal layer. A conductive pad layer and a passivation layer are sequentially located on the interconnecting structure. The testing structure is electrically coupled to the interconnecting structure. The interconnecting structure is also electrically coupled to the conductive pad layer. The grounded metal layer is grounded without any further coupling such that the grounded metal layer is not coupled to the testing structure and the interconnecting structure.

Claims20

Dependent claims

A test key structure, used in a wafer acceptance testing (WAT) method, the test key structure comprising:

a test device structure located on a wafer substrate;
an inter-layer dielectric layer covering over the substrate;
a conductive structure layer located on the inter-layer dielectric layer;
an interconnecting structure located on the conductive structure layer;
a conductive pad layer located on the interconnecting structure;
and
a passivation layer located on the conductive pad layer,
wherein the test device structure is electrically coupled to the interconnect structure, which is further electrically coupled to the conductive pad layer, and the conductive structure layer is grounded without other electrical coupling.

5 more elements

A method to distinguish a plasma damage origin, the method comprising:

providing a first test key, which comprises a first test device structure, a grounded conductive structure, and a first interconnecting structure sequentially located on substrate, wherein the grounded conductive structure is grounded and has no electrical coupling with the first test device structure and the first interconnecting structure;
providing a second test key, which comprises a second test device structure and a second interconnecting structure, with an electrical coupling, sequentially located on the substrate at a location other than the first test key, in which the first test device structure and the second device structure are simultaneously formed by a same first fabrication process, and the first interconnecting structure and the second interconnecting structure are simultaneously formed by a same second fabrication process;
testing the first test key to obtain a first testing result;
testing the second test key to obtain a second result;
and
analyzing the first testing result and the second testing result to distinguish a damage origin.

3 more elements

Dependencies are inferred from the claim text.

Wafer acceptance testing method and structure of a test key used in the method

Life of this patent

Wafer acceptance testing method and structure of a test key used in the method

Life of this patent

Abstract

Claims20