Decoupling capacitor configuration for integrated circuit chip

An integrated circuit chip comprising:

• circuitry defined thereon including device structures and conductive traces for conveying a first power supply voltage, a second power supply voltage, and signal voltages;
• a thin-film capacitor formed over said circuitry and electrically coupled thereto;
• conductive vias formed at least partially through said thin-film capacitor from respective of said conductive traces,
• each of a first group of said conductive vias electrically connected to a first conductive plate of said thin-film capacitor and perforating, without connecting to, a second conductive plate of said thin-film capacitor,
• each of a second group of said conductive vias electrically connected to said second conductive plate;
• and
• plural connection points defined thereon, wherein at least a portion of said first group of conductive vias extend to respective of said connection points, and wherein at least a portion of said second group of said conductive vias perforate, without connecting to, said first conductive plate and extend to respective of said connection points.

An integrated circuit chip comprising:

• circuitry defined thereon including device structures and conductive traces for conveying a first power supply voltage, a second power supply voltage, and signal voltages;
• a thin-film capacitor formed over said circuitry and electrically coupled thereto;
• and
• plural connection points defined thereon, said thin-film capacitor disposed between, but not electrically coupled between, said connection points and said circuitry.

An integrated circuit chip comprising:

• circuitry defined thereon including device structures and conductive traces for conveying a first power supply voltage, a second power supply voltage, and signal voltages;
• a thin-film capacitor formed over said circuitry and electrically coupled thereto;
• plural connection points defined thereon;
• and
• first and second groups of conductive vias formed through said thin-film capacitor from respective of said connection points to respective first and second power supply voltage conveying ones of said conductive traces.

An integrated circuit chip comprising:

• circuitry defined thereon including conductive traces for conveying a first power supply voltage, a second power supply voltage, and signal voltages;
• a thin-film capacitor structure defined over said circuitry;
• plural connection points defined over said thin-film capacitor, wherein said thin-film capacitor is interposed between said conductive traces and said connection points;
• and
• conductive vias formed through said thin-film capacitor structure from respective of said conductive traces to respective of said connection points,
• each of a first group of said conductive vias electrically connected to a first conductive plate of said thin-film capacitor structure and perforating, without connection to, a second conductive plate of said thin-film capacitor structure, and
• each of a second group of said conductive vias electrically connected to said second conductive plate and perforating, without connection to, said first conductive plate.

An integrated circuit chip comprising:

• circuitry defined thereon including conductive traces for conveying a first power supply voltage, a second power supply voltage, and signal voltages;
• a thin-film capacitor structure defined over said circuitry;
• and
• plural connection points defined over said thin-film capacitor;
• wherein said thin-film capacitor is interposed between said conductive traces and said connection points,
• wherein said thin-film capacitor structure includes at least two substantially co-extensive electrodes separated by a dielectric layer;
• wherein a first of said electrodes is connected, via plural electrical paths, to a first group of said conductive traces conveying said first power supply voltage, and wherein said first electrode is further connected to a first group of said connection points via plural electrical paths that perforate, without coupling to, a second of said electrodes;
• and
• wherein said second electrode is connected, via plural electrical paths that perforate without coupling to said first electrode, to a second group of said conductive traces conveying said second power supply voltage, and wherein said second electrode is further connected to a second group of said connection points via plural electrical paths.

An integrated circuit chip comprising:

• circuitry defined thereon including conductive traces for conveying a first power supply voltage, a second power supple voltage, and signal voltages;
• a thin-film capacitor structure defined over said circuitry;
• and
• plural connection points defined over said thin-film capacitor, wherein said thin-film capacitor is interposed between said conductive traces and said connection points,
• wherein said thin-film capacitor structure includes first and second conductive layers with a dielectric layer formed therebetween;
• wherein said first conductive layer is patterned to define first and second distinct electrode regions;
• and
• wherein said second conductive layer includes a common electrode region electrically disposed between said first and second distinct electrode regions to define a series capacitor configuration robust to a short circuit between any two of said first, said second and said common electrode regions.

An apparatus comprising:

• circuitry including power supply voltage conductors defined on an integrated circuit chip;
• power supply voltage connection points defined above said circuity on an upper surface of said integrated circuit chip;
• and
• a decoupling capacitor integral with said integrated circuit chip electrically and physically interposed between said conductors and said connection points;
• and
• first and second groups of conductive vias for conveying respective first and second power supply voltages from respective of said power supply voltage connection points to respective of said power supply voltage conductors,
• wherein the conductive vias of said first group and the conductive vias of said second group each perforate, without connecting to, a respective conductive plate of said decoupling capacitor.

An integrated circuit package configuration comprising:

• a thin-film capacitor;
• conductive vias formed at least partially through said thin-film capacitor and extending to first connection points on a lower surface thereof for coupling to corresponding second connection points of an integrated circuit chip,
• each of a first group of said conductive vias electrically connected to a first conductive plate of said thin-film capacitor and perforating, without connecting to, a second conductive plate of said thin-film capacitor, and
• each of a second group of said conductive vias electrically connected to said second conductive plate and perforating, without connecting to, said first conductive plate.