Semiconductor device including output circuit improved in electrostatic damage resistance

A semiconductor device comprising:

• a first transistor string including a plurality of first transistors aligned with each other in a first direction, each of the first transistors including a first impurity region connected to a first node and second impurity regions connected to a second node and arranged adjacently to both sides of said first impurity region in said first direction;
• and
• a second transistor string arranged adjacently to said first transistor string in a second direction perpendicular to said first direction and including a plurality of second transistors aligned with each other along said first direction, each of said plurality of second transistors of said second transistor string including a third impurity region connected to said first node and fourth impurity regions arranged adjacently to both sides of said third impurity region in said first direction and connected to said second node;
• said plurality of second transistors of said second transistor string being arranged such that the third impurity regions are faced to the second impurity regions of said first transistors of said first transistor string in said second direction, adjacent second transistors in said second transistor string share the fourth impurity regions, and
• one of the first and second nodes being connected to a reference voltage source.

A semiconductor device comprising:

• a first transistor string comprising a plurality of first transistors arranged alignedly with each other along a first direction, each of the first transistors including a first impurity region connected to a reference voltage source and second impurity regions connected to a first node and arranged adjacently to both sides of said first impurity region in said first direction;
• a third impurity region arranged between adjacent first transistors in said first transistor string and connected to said reference voltage source;
• a second transistor string arranged adjacently to said first transistor string in a second direction perpendicular to said first direction and including a plurality of second transistors arranged alignedly with each other along said first direction, each of the second transistors including a fourth impurity region connected to said reference voltage source and fifth impurity regions arranged adjacently to both sides of said fourth impurity region in said first direction and connected to said first node, said plurality of second transistors of said second transistor string being so arranged that the fourth impurity regions face to either said second impurity regions of said plurality of first transistors of said first transistor string or said third impurity region in said second direction;
• and
• a sixth impurity region arranged between adjacent second transistors of said second transistor string to be faced to the second impurity regions of said first transistor string and connected to said reference voltage source.