US 6,191,039 B1 · Method of CMP of polysilicon

Abstract

An improved and new process for fabricating a planarized structure of polysilicon plugs, embedded in silicon oxide has been developed. The planarizing method comprises a two-step CMP process in which the first. CMP step comprises chemical-mechanical polishing using a first polishing slurry which is selective to polysilicon and the second CMP step comprises chemical-mechanical polishing using a second polishing slurry which polishes both polysilicon and silicon oxide. The processing time of the two-step CMP process is significantly less than the processing time of a one-step CMP process requiring an over-polish period. This reduced processing time reduces the cost of the CMP operation and at the same time produces a product with superior planarity and without reliability degradation due to residues of polysilicon.

Claims19

Dependent claims

A method of fabricating a planarized structure on a semiconductor substrate, wherein doped polysilicon plugs are embedded in contact openings in a layer of silicon oxide, the method comprising the following steps:

providing a semiconductor substrate having a layer of silicon oxide deposited thereon and into which are etched contact openings;
providing a layer of doped polysilicon above the layer of silicon oxide and within the contact openings;
chemical-mechanical polishing the layer of doped polysilicon to the layer of silicon oxide by a two-step process, the first CMP step comprising chemical-mechanical polishing using a first polishing slurry which is selective to said doped polysilicon;
and
further chemical-mechanical polishing the layer of doped polysilicon by a second CMP step comprising chemical-mechanical polishing using a second polishing slurry which polishes both the doped polysilicon and the silicon oxide.

2 more elements

Dependencies are inferred from the claim text.

Method of CMP of polysilicon

Life of this patent

Method of CMP of polysilicon

Life of this patent

Abstract

Claims19