Forming minimal size spaces in integrated circuit conductive lines
AssigneeAdvanced Micro Devices, Inc.
InventorsRichard K. Klein, Asim A. Selcuk, Nicholas J. Kepler, Christopher A. Spence, Raymond T. Lee, John C. Holst, Stephen C. Horne
Life of this patent
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Abstract
A method of forming minimal gaps or spaces in conductive lines pattern for increasing the density of integrated circuits by first forming an opening in an insulating layer overlying the conductive line by conventional optical lithography, followed by forming sidewalls in the opening to create a reduced opening, and using the sidewalls as a mask to remove, preferably by etching, a portion of the conductive line pattern substantially equal in size to the reduced opening.
Claims12
In a method of fabricating a gap or space in a conductive line pattern of an integrated circuit, the method comprising the steps of:
- forming the conductive line pattern, for interconnecting transistors in the integrated circuit, disposed on a semiconductor substrate;
- forming an etch protective layer on said conductive line pattern;
- forming an insulating layer on said etch protective layer;
- forming, using optical lithography, an opening with vertical walls in said insulating layer to expose said conductive line pattern for creating an open in the conductive line pattern;
- depositing, a conformal material on said insulating layer, on the vertical walls of said opening and on said exposed conductive line pattern;
- forming sidewalls from the conformal material on the vertical walls of said opening to substantially reduce the opening to form a reduced opening by the addition of the sidewalls;
- completely removing a portion of the conductive line pattern of about the same size as the reduced opening by using the sidewalls as a mask to from the gap or space in the conductive line pattern to serve as an open in the conductive line pattern, whereby the gap or space is smaller in dimension than the opening created by optical lithography;
- and
- maintaining the size of said gap or space in said conductive line pattern during the remaining fabrication of the conductive line pattern.
A method of fabricating a gap or space in a conductive line pattern for connecting transistors in an integrated circuit comprising the steps of:
- forming the conductive line pattern with a thickness, disposed on a semiconductor substrate and overlying and in contact with field oxide isolation in the substrate;
- forming an etch protective layer on said conductive pattern;
- forming an insulating layer on said each protective layer;
- forming an opening in said insulating layer over said field oxide isolation using optical lithography;
- depositing a conformal material on said insulating layer and in said opening;
- forming sidewalls of the conformal material in said opening with a reduced opening between the sidewalls;
- and
- removing completely through its thickness a portion of the conductive line pattern of about the same size as the reduced opening by using the sidewalls as a mask and said field oxide isolation as an etch stop to from the gap or space in the conductive line pattern over the field oxide isolation, whereby the gap or space is smaller in dimension than the opening created by optical lithography.
Dependencies are inferred from the claim text.